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hv: nested: setup emulated VMX MSRs
We emulated these MSRs: - MSR_IA32_VMX_PINBASED_CTLS - MSR_IA32_VMX_PROCBASED_CTLS - MSR_IA32_VMX_PROCBASED_CTLS2 - MSR_IA32_VMX_EXIT_CTLS - MSR_IA32_VMX_ENTRY_CTLS - MSR_IA32_VMX_BASIC: emulate VMCS revision ID, etc. - MSR_IA32_VMX_MISC For the following MSRs, we pass through the physical value to L1 guests: - MSR_IA32_VMX_EPT_VPID_CAP - MSR_IA32_VMX_VMCS_ENUM - MSR_IA32_VMX_CR0_FIXED0 - MSR_IA32_VMX_CR0_FIXED1 - MSR_IA32_VMX_CR4_FIXED0 - MSR_IA32_VMX_CR4_FIXED1 Tracked-On: #5923 Signed-off-by: Zide Chen <zide.chen@intel.com> Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Zide Chen
wenlingz
parent
4930992118
commit
c9982e8c7e
@ -30,24 +30,189 @@ bool is_vmx_msr(uint32_t msr)
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return found;
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}
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/*
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* @pre vcpu != NULL
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*/
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void init_vmx_msrs(__unused struct acrn_vcpu *vcpu)
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static uint64_t adjust_vmx_ctrls(uint32_t msr, uint64_t request_bits)
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{
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/* implemented in next patch */
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union value_64 val64, msr_val;
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/*
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* ISDM Appendix A.3, A.4, A.5:
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* - Bits 31:0 indicate the allowed 0-settings of these controls.
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* bit X of the corresponding VM-execution controls field is allowed to be 0
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* if bit X in the MSR is cleared to 0
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* - Bits 63:32 indicate the allowed 1-settings of these controls.
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* VM entry allows control X to be 1 if bit 32+X in the MSR is set to 1
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*/
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msr_val.full = msr_read(msr);
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/*
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* The reserved bits in VMCS Control fields could be 0 or 1, determined by the
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* corresponding capability MSR. So need to read them from physical MSR.
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*
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* We consider the bits that are set in the allowed 0-settings group as the
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* minimal set of bits that need to be set from the physical processor's perspective.
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* Since we shadow this control field, we passthru the allowed 0-settings bits.
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*/
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val64.u.lo_32 = msr_val.u.lo_32;
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/* allowed 1-settings include those bits are NOT allowed to be 0 */
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val64.u.hi_32 = msr_val.u.lo_32;
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/* make sure the requested features are supported by hardware */
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val64.u.hi_32 |= (msr_val.u.hi_32 & request_bits);
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return val64.full;
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}
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/*
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* @pre vcpu != NULL
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*/
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int32_t read_vmx_msr(struct acrn_vcpu *vcpu, __unused uint32_t msr, uint64_t *val)
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void init_vmx_msrs(struct acrn_vcpu *vcpu)
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{
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union value_64 val64;
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uint64_t request_bits, msr_value;
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if (is_nvmx_configured(vcpu->vm)) {
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/* MSR_IA32_VMX_BASIC */
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val64.full = VMCS12_REVISION_ID /* Bits 30:0 - VMCS revision ID */
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| (4096UL << 32U) /* Bits 44:32 - size of VMXON region and VMCS region */
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| (6UL << 50U) /* Bits 53:50 - memory type for VMCS etc. (6: Write Back) */
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| (1UL << 54U) /* Bit 54: VM-exit instruction-information for INS and OUTS */
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| (1UL << 55U); /* Bit 55: VMX controls that default to 1 may be cleared to 0 */
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vcpu_set_guest_msr(vcpu, MSR_IA32_VMX_BASIC, val64.full);
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/* MSR_IA32_VMX_MISC */
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/*
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* some bits need to read from physical MSR. For exmaple Bits 4:0 report the relationship between
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* the rate of the VMX-preemption timer and that of the timestamp counter (TSC).
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*/
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val64.full = msr_read(MSR_IA32_VMX_MISC);
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val64.u.hi_32 = 0U;
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/* Don't support Intel® Processor Trace (Intel PT) in VMX operation */
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val64.u.lo_32 &= ~(1U << 14U);
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/* Don't support SMM in VMX operation */
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val64.u.lo_32 &= ~((1U << 15U) | (1U << 28U));
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vcpu_set_guest_msr(vcpu, MSR_IA32_VMX_MISC, val64.full);
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/*
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* TODO: These emulated VMX Control MSRs work for Tiger Lake and Kaby Lake,
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* potentially it may have problems if run on other platforms.
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*
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* We haven't put our best efforts to try to enable as much as features as
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* possible.
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*/
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/* MSR_IA32_VMX_PINBASED_CTLS */
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request_bits = VMX_PINBASED_CTLS_IRQ_EXIT
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| VMX_PINBASED_CTLS_NMI_EXIT
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| VMX_PINBASED_CTLS_ENABLE_PTMR;
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msr_value = adjust_vmx_ctrls(MSR_IA32_VMX_PINBASED_CTLS, request_bits);
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vcpu_set_guest_msr(vcpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS, msr_value);
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vcpu_set_guest_msr(vcpu, MSR_IA32_VMX_PINBASED_CTLS, msr_value);
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/* MSR_IA32_VMX_PROCBASED_CTLS */
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request_bits = VMX_PROCBASED_CTLS_IRQ_WIN | VMX_PROCBASED_CTLS_TSC_OFF
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| VMX_PROCBASED_CTLS_HLT | VMX_PROCBASED_CTLS_INVLPG
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| VMX_PROCBASED_CTLS_MWAIT | VMX_PROCBASED_CTLS_RDPMC
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| VMX_PROCBASED_CTLS_RDTSC | VMX_PROCBASED_CTLS_CR3_LOAD
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| VMX_PROCBASED_CTLS_CR3_STORE | VMX_PROCBASED_CTLS_CR8_LOAD
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| VMX_PROCBASED_CTLS_CR8_STORE | VMX_PROCBASED_CTLS_NMI_WINEXIT
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| VMX_PROCBASED_CTLS_MOV_DR | VMX_PROCBASED_CTLS_UNCOND_IO
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| VMX_PROCBASED_CTLS_MSR_BITMAP | VMX_PROCBASED_CTLS_MONITOR
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| VMX_PROCBASED_CTLS_PAUSE | VMX_PROCBASED_CTLS_SECONDARY;
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msr_value = adjust_vmx_ctrls(MSR_IA32_VMX_PROCBASED_CTLS, request_bits);
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vcpu_set_guest_msr(vcpu, MSR_IA32_VMX_PROCBASED_CTLS, msr_value);
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vcpu_set_guest_msr(vcpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS, msr_value);
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/* MSR_IA32_VMX_PROCBASED_CTLS2 */
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request_bits = VMX_PROCBASED_CTLS2_EPT | VMX_PROCBASED_CTLS2_RDTSCP
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| VMX_PROCBASED_CTLS2_VPID | VMX_PROCBASED_CTLS2_WBINVD
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| VMX_PROCBASED_CTLS2_UNRESTRICT | VMX_PROCBASED_CTLS2_PAUSE_LOOP
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| VMX_PROCBASED_CTLS2_RDRAND | VMX_PROCBASED_CTLS2_INVPCID
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| VMX_PROCBASED_CTLS2_RDSEED | VMX_PROCBASED_CTLS2_XSVE_XRSTR
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| VMX_PROCBASED_CTLS2_PT_USE_GPA | VMX_PROCBASED_CTLS2_TSC_SCALING;
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msr_value = adjust_vmx_ctrls(MSR_IA32_VMX_PROCBASED_CTLS2, request_bits);
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vcpu_set_guest_msr(vcpu, MSR_IA32_VMX_PROCBASED_CTLS2, msr_value);
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/* MSR_IA32_VMX_EXIT_CTLS */
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request_bits = VMX_EXIT_CTLS_SAVE_DBG | VMX_EXIT_CTLS_HOST_ADDR64
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| VMX_EXIT_CTLS_ACK_IRQ | VMX_EXIT_CTLS_LOAD_PAT
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| VMX_EXIT_CTLS_LOAD_EFER;
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msr_value = adjust_vmx_ctrls(MSR_IA32_VMX_EXIT_CTLS, request_bits);
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vcpu_set_guest_msr(vcpu, MSR_IA32_VMX_EXIT_CTLS, msr_value);
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vcpu_set_guest_msr(vcpu, MSR_IA32_VMX_TRUE_EXIT_CTLS, msr_value);
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/* MSR_IA32_VMX_ENTRY_CTLS */
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request_bits = VMX_ENTRY_CTLS_LOAD_DBG | VMX_ENTRY_CTLS_IA32E_MODE
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| VMX_ENTRY_CTLS_LOAD_PERF | VMX_ENTRY_CTLS_LOAD_PAT
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| VMX_ENTRY_CTLS_LOAD_EFER;
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msr_value = adjust_vmx_ctrls(MSR_IA32_VMX_ENTRY_CTLS, request_bits);
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vcpu_set_guest_msr(vcpu, MSR_IA32_VMX_ENTRY_CTLS, msr_value);
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vcpu_set_guest_msr(vcpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS, msr_value);
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/* For now passthru the value from physical MSR to L1 guest */
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msr_value = msr_read(MSR_IA32_VMX_EPT_VPID_CAP);
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vcpu_set_guest_msr(vcpu, MSR_IA32_VMX_EPT_VPID_CAP, msr_value);
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msr_value = msr_read(MSR_IA32_VMX_CR0_FIXED0);
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vcpu_set_guest_msr(vcpu, MSR_IA32_VMX_CR0_FIXED0, msr_value);
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msr_value = msr_read(MSR_IA32_VMX_CR0_FIXED1);
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vcpu_set_guest_msr(vcpu, MSR_IA32_VMX_CR0_FIXED1, msr_value);
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msr_value = msr_read(MSR_IA32_VMX_CR4_FIXED0);
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vcpu_set_guest_msr(vcpu, MSR_IA32_VMX_CR4_FIXED0, msr_value);
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msr_value = msr_read(MSR_IA32_VMX_CR4_FIXED1);
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vcpu_set_guest_msr(vcpu, MSR_IA32_VMX_CR4_FIXED1, msr_value);
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msr_value = msr_read(MSR_IA32_VMX_VMCS_ENUM);
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vcpu_set_guest_msr(vcpu, MSR_IA32_VMX_VMCS_ENUM, msr_value);
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}
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}
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/*
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* @pre vcpu != NULL
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*/
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int32_t read_vmx_msr(struct acrn_vcpu *vcpu, uint32_t msr, uint64_t *val)
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{
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uint64_t v = 0UL;
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int32_t err = 0;
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if (is_nvmx_configured(vcpu->vm)) {
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/* implemented in next patch */
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switch (msr) {
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case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
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case MSR_IA32_VMX_PINBASED_CTLS:
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case MSR_IA32_VMX_PROCBASED_CTLS:
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case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
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case MSR_IA32_VMX_PROCBASED_CTLS2:
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case MSR_IA32_VMX_EXIT_CTLS:
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case MSR_IA32_VMX_TRUE_EXIT_CTLS:
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case MSR_IA32_VMX_ENTRY_CTLS:
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case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
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case MSR_IA32_VMX_BASIC:
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case MSR_IA32_VMX_MISC:
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case MSR_IA32_VMX_EPT_VPID_CAP:
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case MSR_IA32_VMX_CR0_FIXED0:
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case MSR_IA32_VMX_CR0_FIXED1:
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case MSR_IA32_VMX_CR4_FIXED0:
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case MSR_IA32_VMX_CR4_FIXED1:
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case MSR_IA32_VMX_VMCS_ENUM:
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{
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v = vcpu_get_guest_msr(vcpu, msr);
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break;
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}
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/* Don't support these MSRs yet */
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case MSR_IA32_SMBASE:
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case MSR_IA32_VMX_PROCBASED_CTLS3:
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case MSR_IA32_VMX_VMFUNC:
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default:
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err = -EACCES;
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break;
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}
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} else {
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err = -EACCES;
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}
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@ -8,6 +8,15 @@
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#include <lib/errno.h>
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/* helper data structure to make VMX capability MSR manipulation easier */
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union value_64 {
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uint64_t full;
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struct {
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uint32_t lo_32;
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uint32_t hi_32;
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} u;
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};
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/*
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* Following MSRs are supported if nested virtualization is enabled
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* - If CONFIG_NVMX_ENABLED is set, these MSRs are included in emulated_guest_msrs[]
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@ -36,6 +45,12 @@
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MSR_IA32_VMX_VMFUNC, \
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MSR_IA32_VMX_PROCBASED_CTLS3
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/*
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* This VMCS12 revision id is chosen arbitrarily.
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* The emulated MSR_IA32_VMX_BASIC returns this ID in bits 30:0.
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*/
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#define VMCS12_REVISION_ID 0x15407E12U
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#ifdef CONFIG_NVMX_ENABLED
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bool is_vmx_msr(uint32_t msr);
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void init_vmx_msrs(struct acrn_vcpu *vcpu);
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@ -314,10 +314,15 @@
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#define VMX_PROCBASED_CTLS2_INVPCID (1U<<12U)
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#define VMX_PROCBASED_CTLS2_VM_FUNCS (1U<<13U)
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#define VMX_PROCBASED_CTLS2_VMCS_SHADW (1U<<14U)
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#define VMX_PROCBASED_CTLS2_ENCLS_EXIT (1U<<15U)
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#define VMX_PROCBASED_CTLS2_RDSEED (1U<<16U)
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#define VMX_PROCBASED_CTLS2_PML (1U<<17U)
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#define VMX_PROCBASED_CTLS2_EPT_VE (1U<<18U)
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#define VMX_PROCBASED_CTLS2_XSVE_XRSTR (1U<<20U)
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#define VMX_PROCBASED_CTLS2_PT_USE_GPA (1U<<22U)
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#define VMX_PROCBASED_CTLS2_TSC_SCALING (1U<<25U)
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#define VMX_PROCBASED_CTLS2_UWAIT_PAUSE (1U<<26U)
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#define VMX_PROCBASED_CTLS2_ENCLV_EXIT (1U<<28U)
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#define VMX_PROCBASED_CTLS3_LOADIWKEY (1U<<0U)
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/* MSR_IA32_VMX_EPT_VPID_CAP: EPT and VPID capability bits */
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