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HV: VPCI coding style fix

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- Converted MACROS to functions
- Defined pci_bar_type enum
- Defined pci_bdf as union instead of uint16_t to eliminate macros
- Use L or UL postfix after unsigned integers

Tracked-On: #1126
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
This commit is contained in:
dongshen
2018-08-28 11:39:32 -07:00
committed by lijinxia
parent 54439ecae1
commit c9ea8901e6
7 changed files with 140 additions and 146 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
hypervisor/dm/vpci/hostbridge.c
View File

@@ -97,8 +97,8 @@ static int vdev_hostbridge_cfgread(struct pci_vdev *vdev, uint32_t offset,
uint32_t bytes, uint32_t *val)
{
/* Assumption: access needed to be aligned on 1/2/4 bytes */
if ((offset & (bytes - 1)) != 0U) {
*val = 0xffffffffU;
if ((offset & (bytes - 1U)) != 0U) {
*val = 0xFFFFFFFFU;
return -EINVAL;
}
@@ -111,7 +111,7 @@ static int vdev_hostbridge_cfgwrite(struct pci_vdev *vdev, uint32_t offset,
uint32_t bytes, uint32_t val)
{
/* Assumption: access needed to be aligned on 1/2/4 bytes */
if ((offset & (bytes - 1)) != 0U) {
if ((offset & (bytes - 1U)) != 0U) {
return -EINVAL;
}
@@ -123,7 +123,7 @@ static int vdev_hostbridge_cfgwrite(struct pci_vdev *vdev, uint32_t offset,
struct pci_vdev_ops pci_ops_vdev_hostbridge = {
.init = vdev_hostbridge_init,
.deinit = vdev_hostbridge_deinit,
.cfgwrite = vdev_hostbridge_cfgwrite,
.cfgread = vdev_hostbridge_cfgread,
.cfgwrite = vdev_hostbridge_cfgwrite,
};

52
hypervisor/dm/vpci/pci_priv.h
View File

@@ -33,50 +33,33 @@
#include <hv_debug.h>
#include "vpci.h"
#define PCIM_BAR_MEM_BASE 0xfffffff0U
#define PCI_BAR_BASE(val) ((val) & PCIM_BAR_MEM_BASE)
#define PCI_BAR(base, type) ((base) | (type))
#define PCIM_BAR_MEM_BASE 0xFFFFFFF0U
#define PCI_BUS(bdf) (((bdf) >> 8) & 0xFFU)
#define PCI_SLOT(bdf) (((bdf) >> 3) & 0x1FU)
#define PCI_FUNC(bdf) ((bdf) & 0x07U)
#define LOBYTE(w) ((uint8_t)((w) & 0xffU))
#define PCI_BUSMAX 0xffU
#define PCI_SLOTMAX 0x1fU
#define PCI_BUSMAX 0xFFU
#define PCI_SLOTMAX 0x1FU
#define PCI_FUNCMAX 0x7U
#define MAXBUSES (PCI_BUSMAX + 1U)
#define MAXSLOTS (PCI_SLOTMAX + 1U)
#define MAXFUNCS (PCI_FUNCMAX + 1U)
#define PCIR_VENDOR 0x00U
#define PCIR_DEVICE 0x02U
#define PCIR_COMMAND 0x04U
#define PCIM_CMD_MEMEN 0x0002U
#define PCIR_REVID 0x08U
#define PCIR_SUBCLASS 0x0aU
#define PCIR_CLASS 0x0bU
#define PCIR_HDRTYPE 0x0eU
#define PCIR_SUBCLASS 0x0AU
#define PCIR_CLASS 0x0BU
#define PCIR_HDRTYPE 0x0EU
#define PCIM_HDRTYPE_NORMAL 0x00U
#define PCIM_MFDEV 0x80U
#define PCIR_BARS 0x10U
#define PCIR_BAR(x) (PCIR_BARS + ((x) * 4U))
#define PCIM_BAR_MEM_SPACE 0U
#define PCIC_BRIDGE 0x06U
#define PCIS_BRIDGE_HOST 0x00U
#define PCI_CONFIG_ADDR 0xcf8U
#define PCI_CONFIG_DATA 0xcfcU
#define PCI_CONFIG_ADDR 0xCF8U
#define PCI_CONFIG_DATA 0xCFCU
#define PCI_CFG_ENABLE 0x80000000U
void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in, uint16_t vbdf,
uint32_t offset, uint32_t bytes, uint32_t *val);
void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in,
union pci_bdf vbdf, uint32_t offset, uint32_t bytes, uint32_t *val);
static inline uint8_t
pci_vdev_read_cfg_u8(struct pci_vdev *vdev, uint32_t offset)
@@ -150,4 +133,19 @@ static inline void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset,
}
}
static inline uint32_t pci_bar_offset(uint32_t idx)
{
return 0x10U + (idx << 2U);
}
static inline int pci_bar_access(uint32_t offset)
{
if ((offset >= pci_bar_offset(0U))
&& (offset < pci_bar_offset(PCI_BAR_COUNT))) {
return 1;
} else {
return 0;
}
}
#endif /* PCI_PRIV_H_ */

88
hypervisor/dm/vpci/pci_pt.c
View File

@@ -40,13 +40,17 @@
static spinlock_t pci_device_lock = { .head = 0, .tail = 0 };
static uint32_t pci_pdev_calc_address(uint16_t bdf, uint32_t offset)
static inline uint32_t pci_bar_base(uint32_t bar)
{
uint32_t addr = bdf;
return bar & PCIM_BAR_MEM_BASE;
}
addr <<= 8;
static uint32_t pci_pdev_calc_address(union pci_bdf bdf, uint32_t offset)
{
uint32_t addr = (uint32_t)bdf.value;
addr <<= 8U;
addr |= (offset | PCI_CFG_ENABLE);
return addr;
}
@@ -61,7 +65,7 @@ static uint32_t pci_pdev_read_cfg(struct pci_pdev *pdev,
addr = pci_pdev_calc_address(pdev->bdf, offset);
/* Write address to ADDRESS register */
pio_write(addr, PCI_CONFIG_ADDR, 4);
pio_write(addr, PCI_CONFIG_ADDR, 4U);
/* Read result from DATA register */
switch (bytes) {
@@ -90,7 +94,7 @@ static void pci_pdev_write_cfg(struct pci_pdev *pdev, uint32_t offset,
addr = pci_pdev_calc_address(pdev->bdf, offset);
/* Write address to ADDRESS register */
pio_write(addr, PCI_CONFIG_ADDR, 4);
pio_write(addr, PCI_CONFIG_ADDR, 4U);
/* Write value to DATA register */
switch (bytes) {
@@ -112,7 +116,10 @@ static int vdev_pt_init_validate(struct pci_vdev *vdev)
uint32_t idx;
for (idx = 0; idx < (uint32_t)PCI_BAR_COUNT; idx++) {
if (vdev->bar[idx].type != PCIM_BAR_MEM_32) {
if ((vdev->bar[idx].base != 0x0UL)
|| ((vdev->bar[idx].size & 0xFFFUL) != 0x0UL)
|| ((vdev->bar[idx].type != PCIBAR_MEM32)
&& (vdev->bar[idx].type != PCIBAR_NONE))) {
return -EINVAL;
}
}
@@ -120,17 +127,6 @@ static int vdev_pt_init_validate(struct pci_vdev *vdev)
return 0;
}
static void vdev_pt_init_bar_registers(struct pci_vdev *vdev)
{
uint32_t idx;
for (idx = 0; idx < (uint32_t)PCI_BAR_COUNT; idx++) {
/* Initialize the BAR register in config space */
pci_vdev_write_cfg_u32(vdev, PCIR_BAR(idx),
PCI_BAR(vdev->bar[idx].base, vdev->bar[idx].type));
}
}
static int vdev_pt_init(struct pci_vdev *vdev)
{
int ret;
@@ -138,7 +134,7 @@ static int vdev_pt_init(struct pci_vdev *vdev)
ret = vdev_pt_init_validate(vdev);
if (ret != 0) {
pr_err("virtual bar can only be of type PCIM_BAR_MEM_32!");
pr_err("Error, invalid bar defined");
return ret;
}
@@ -151,10 +147,8 @@ static int vdev_pt_init(struct pci_vdev *vdev)
HVA2HPA(vm->arch_vm.nworld_eptp), 48U);
}
ret = assign_iommu_device(vm->iommu,
PCI_BUS(vdev->pdev.bdf), LOBYTE(vdev->pdev.bdf));
vdev_pt_init_bar_registers(vdev);
ret = assign_iommu_device(vm->iommu, vdev->pdev.bdf.bits.b,
(uint8_t)(vdev->pdev.bdf.value & 0xFFU));
return ret;
}
@@ -164,32 +158,23 @@ static int vdev_pt_deinit(struct pci_vdev *vdev)
int ret;
struct vm *vm = vdev->vpci->vm;
ret = unassign_iommu_device(vm->iommu, PCI_BUS(vdev->pdev.bdf),
LOBYTE(vdev->pdev.bdf));
ret = unassign_iommu_device(vm->iommu, vdev->pdev.bdf.bits.b,
(uint8_t)(vdev->pdev.bdf.value & 0xFFU));
return ret;
}
static int bar_access(uint32_t coff)
{
if ((coff >= PCIR_BAR(0U)) && (coff < PCIR_BAR(PCI_BAR_COUNT))) {
return 1;
} else {
return 0;
}
}
static int vdev_pt_cfgread(struct pci_vdev *vdev, uint32_t offset,
uint32_t bytes, uint32_t *val)
{
/* Assumption: access needed to be aligned on 1/2/4 bytes */
if ((offset & (bytes - 1)) != 0U) {
*val = 0xffffffffU;
if ((offset & (bytes - 1U)) != 0U) {
*val = 0xFFFFFFFFU;
return -EINVAL;
}
/* PCI BARs is emulated */
if (bar_access(offset)) {
if (pci_bar_access(offset)) {
*val = pci_vdev_read_cfg(vdev, offset, bytes);
} else {
*val = pci_pdev_read_cfg(&vdev->pdev, offset, bytes);
@@ -204,11 +189,11 @@ static int vdev_pt_remap_bar(struct pci_vdev *vdev, uint32_t idx,
int error = 0;
struct vm *vm = vdev->vpci->vm;
if (vdev->bar[idx].base != 0) {
if (vdev->bar[idx].base != 0UL) {
error = ept_mr_del(vm, (uint64_t *)vm->arch_vm.nworld_eptp,
vdev->bar[idx].base,
vdev->bar[idx].size);
if (error) {
if (error != 0) {
return error;
}
}
@@ -220,7 +205,7 @@ static int vdev_pt_remap_bar(struct pci_vdev *vdev, uint32_t idx,
new_base, /*GPA*/
vdev->bar[idx].size,
EPT_WR | EPT_RD | EPT_UNCACHED);
if (error) {
if (error != 0) {
return error;
}
}
@@ -229,7 +214,7 @@ static int vdev_pt_remap_bar(struct pci_vdev *vdev, uint32_t idx,
static uint32_t memen(struct pci_vdev *vdev)
{
return pci_pdev_read_cfg(&vdev->pdev, PCIR_COMMAND, 2)
return pci_pdev_read_cfg(&vdev->pdev, PCIR_COMMAND, 2U)
& PCIM_CMD_MEMEN;
}
@@ -242,38 +227,41 @@ static void vdev_pt_cfgwrite_bar(struct pci_vdev *vdev, uint32_t offset,
bool do_map;
int error;
idx = (offset - PCIR_BAR(0U)) >> 2U;
if ((bytes != 4U) || ((offset & 0x3U) != 0U)) {
return;
}
idx = (offset - pci_bar_offset(0U)) >> 2U;
mask = ~(vdev->bar[idx].size - 1U);
bar_update_normal = (new_bar_uos != (uint32_t)~0U);
new_bar = new_bar_uos & mask;
new_bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
if (PCI_BAR_BASE(new_bar) == vdev->bar[idx].base) {
if (pci_bar_base(new_bar) == vdev->bar[idx].base) {
return;
}
do_map = (memen(vdev)) && bar_update_normal;
if (do_map) {
error = vdev_pt_remap_bar(vdev, idx, PCI_BAR_BASE(new_bar));
if (error) {
error = vdev_pt_remap_bar(vdev, idx, pci_bar_base(new_bar));
if (error != 0) {
pr_err("vdev_pt_remap_bar failed: %d", idx);
}
}
pci_vdev_write_cfg_u32(vdev, offset, new_bar);
vdev->bar[idx].base = PCI_BAR_BASE(new_bar);
vdev->bar[idx].base = pci_bar_base(new_bar);
}
static int vdev_pt_cfgwrite(struct pci_vdev *vdev, uint32_t offset,
uint32_t bytes, uint32_t val)
{
/* Assumption: access needed to be aligned on 1/2/4 bytes */
if ((offset & (bytes - 1)) != 0U) {
if ((offset & (bytes - 1U)) != 0U) {
return -EINVAL;
}
/* PCI BARs are emulated */
if (bar_access(offset)) {
if (pci_bar_access(offset)) {
vdev_pt_cfgwrite_bar(vdev, offset, bytes, val);
} else {
/* Write directly to physical device's config space */
@@ -286,7 +274,7 @@ static int vdev_pt_cfgwrite(struct pci_vdev *vdev, uint32_t offset,
struct pci_vdev_ops pci_ops_vdev_pt = {
.init = vdev_pt_init,
.deinit = vdev_pt_deinit,
.cfgwrite = vdev_pt_cfgwrite,
.cfgread = vdev_pt_cfgread,
.cfgwrite = vdev_pt_cfgwrite,
};

10
hypervisor/dm/vpci/pci_vdev.c
View File

@@ -38,7 +38,7 @@
#include "pci_priv.h"
static struct pci_vdev *pci_vdev_find(struct vpci *vpci, uint16_t vbdf)
static struct pci_vdev *pci_vdev_find(struct vpci *vpci, union pci_bdf vbdf)
{
struct vpci_vdev_array *vdev_array;
struct pci_vdev *vdev;
@@ -47,7 +47,7 @@ static struct pci_vdev *pci_vdev_find(struct vpci *vpci, uint16_t vbdf)
vdev_array = vpci->vm->vm_desc->vpci_vdev_array;
for (i = 0; i < vdev_array->num_pci_vdev; i++) {
vdev = &vdev_array->vpci_vdev_list[i];
if (vdev->vbdf == vbdf) {
if (vdev->vbdf.value == vbdf.value) {
return vdev;
}
}
@@ -56,7 +56,7 @@ static struct pci_vdev *pci_vdev_find(struct vpci *vpci, uint16_t vbdf)
}
/* PCI cfg vm-exit handler */
void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in, uint16_t vbdf,
void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in, union pci_bdf vbdf,
uint32_t offset, uint32_t bytes, uint32_t *val)
{
struct pci_vdev *vdev;
@@ -68,7 +68,7 @@ void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in, uint16_t vbdf,
}
ret = -EINVAL;
if (in) {
if (in == 1U) {
if ((vdev->ops != NULL) && (vdev->ops->cfgread != NULL)) {
ret = vdev->ops->cfgread(vdev, offset, bytes, val);
}
@@ -78,7 +78,7 @@ void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in, uint16_t vbdf,
}
}
if (ret) {
if (ret != 0) {
pr_dbg("pci_vdev_cfg_handler failed, ret=%d", ret);
}
}

38
hypervisor/dm/vpci/vpci.c
View File

@@ -37,17 +37,17 @@
static bool is_cfg_addr(uint16_t addr)
{
return (addr >= PCI_CONFIG_ADDR) && (addr < (PCI_CONFIG_ADDR + 4));
return (addr >= PCI_CONFIG_ADDR) && (addr < (PCI_CONFIG_ADDR + 4U));
}
static bool is_cfg_data(uint16_t addr)
{
return (addr >= PCI_CONFIG_DATA) && (addr < (PCI_CONFIG_DATA + 4));
return (addr >= PCI_CONFIG_DATA) && (addr < (PCI_CONFIG_DATA + 4U));
}
static void pci_cfg_clear_cache(struct pci_addr_info *pi)
{
pi->cached_bdf = 0xffffU;
pi->cached_bdf.value = 0xFFFFU;
pi->cached_reg = 0U;
pi->cached_enable = 0U;
}
@@ -55,33 +55,31 @@ static void pci_cfg_clear_cache(struct pci_addr_info *pi)
static uint32_t pci_cfg_io_read(__unused struct vm_io_handler *hdlr,
struct vm *vm, uint16_t addr, size_t bytes)
{
uint32_t val = 0xffffffffU;
uint32_t val = 0xFFFFFFFFU;
struct vpci *vpci = &vm->vpci;
struct pci_addr_info *pi = &vpci->addr_info;
if (is_cfg_addr(addr)) {
/* TODO: handling the non 4 bytes access */
if (bytes == 4U) {
val = (PCI_BUS(pi->cached_bdf) << 16)
| (PCI_SLOT(pi->cached_bdf) << 11)
| (PCI_FUNC(pi->cached_bdf) << 8)
| pi->cached_reg;
val = (uint32_t)pi->cached_bdf.value;
val <<= 8U;
val |= pi->cached_reg;
if (pi->cached_enable) {
val |= PCI_CFG_ENABLE;
}
}
} else if (is_cfg_data(addr)) {
if (pi->cached_enable) {
uint16_t offset = addr - 0xcfc;
uint16_t offset = addr - PCI_CONFIG_DATA;
pci_vdev_cfg_handler(&vm->vpci, 1U, pi->cached_bdf,
pci_vdev_cfg_handler(vpci, 1U, pi->cached_bdf,
pi->cached_reg + offset, bytes, &val);
pci_cfg_clear_cache(pi);
}
} else {
val = 0xffffffffU;
val = 0xFFFFFFFFU;
}
return val;
@@ -96,10 +94,9 @@ static void pci_cfg_io_write(__unused struct vm_io_handler *hdlr,
if (is_cfg_addr(addr)) {
/* TODO: handling the non 4 bytes access */
if (bytes == 4U) {
pi->cached_bdf = PCI_BDF(
((val >> 16) & PCI_BUSMAX),
((val >> 11) & PCI_SLOTMAX),
((val >> 8) & PCI_FUNCMAX));
pi->cached_bdf.bits.b = (val >> 16U) & PCI_BUSMAX;
pi->cached_bdf.bits.d = (val >> 11U) & PCI_SLOTMAX;
pi->cached_bdf.bits.f = (val >> 8U) & PCI_FUNCMAX;
pi->cached_reg = val & PCI_REGMAX;
pi->cached_enable =
@@ -107,9 +104,9 @@ static void pci_cfg_io_write(__unused struct vm_io_handler *hdlr,
}
} else if (is_cfg_data(addr)) {
if (pi->cached_enable) {
uint16_t offset = addr - 0xcfc;
uint16_t offset = addr - PCI_CONFIG_DATA;
pci_vdev_cfg_handler(&vm->vpci, 0U, pi->cached_bdf,
pci_vdev_cfg_handler(vpci, 0U, pi->cached_bdf,
pi->cached_reg + offset, bytes, &val);
pci_cfg_clear_cache(pi);
@@ -136,9 +133,10 @@ void vpci_init(struct vm *vm)
for (i = 0; i < vdev_array->num_pci_vdev; i++) {
vdev = &vdev_array->vpci_vdev_list[i];
vdev->vpci = vpci;
if ((vdev->ops != NULL) && (vdev->ops->init != NULL)) {
ret = vdev->ops->init(vdev);
if (ret) {
if (ret != 0) {
pr_err("vdev->ops->init failed!");
}
}
@@ -161,7 +159,7 @@ void vpci_cleanup(struct vm *vm)
vdev = &vdev_array->vpci_vdev_list[i];
if ((vdev->ops != NULL) && (vdev->ops->deinit != NULL)) {
ret = vdev->ops->deinit(vdev);
if (ret) {
if (ret != 0) {
pr_err("vdev->ops->deinit failed!");
}
}