mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-20 12:42:54 +00:00
HV: VPCI coding style fix
- Converted MACROS to functions - Defined pci_bar_type enum - Defined pci_bdf as union instead of uint16_t to eliminate macros - Use L or UL postfix after unsigned integers Tracked-On: #1126 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
This commit is contained in:
dongshen
lijinxia
parent
54439ecae1
commit
c9ea8901e6
@ -97,8 +97,8 @@ static int vdev_hostbridge_cfgread(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t *val)
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{
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/* Assumption: access needed to be aligned on 1/2/4 bytes */
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if ((offset & (bytes - 1)) != 0U) {
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*val = 0xffffffffU;
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if ((offset & (bytes - 1U)) != 0U) {
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*val = 0xFFFFFFFFU;
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return -EINVAL;
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}
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@ -111,7 +111,7 @@ static int vdev_hostbridge_cfgwrite(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t val)
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{
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/* Assumption: access needed to be aligned on 1/2/4 bytes */
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if ((offset & (bytes - 1)) != 0U) {
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if ((offset & (bytes - 1U)) != 0U) {
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return -EINVAL;
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}
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@ -123,7 +123,7 @@ static int vdev_hostbridge_cfgwrite(struct pci_vdev *vdev, uint32_t offset,
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struct pci_vdev_ops pci_ops_vdev_hostbridge = {
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.init = vdev_hostbridge_init,
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.deinit = vdev_hostbridge_deinit,
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.cfgwrite = vdev_hostbridge_cfgwrite,
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.cfgread = vdev_hostbridge_cfgread,
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.cfgwrite = vdev_hostbridge_cfgwrite,
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};
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@ -33,50 +33,33 @@
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#include <hv_debug.h>
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#include "vpci.h"
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#define PCIM_BAR_MEM_BASE 0xfffffff0U
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#define PCI_BAR_BASE(val) ((val) & PCIM_BAR_MEM_BASE)
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#define PCI_BAR(base, type) ((base) | (type))
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#define PCIM_BAR_MEM_BASE 0xFFFFFFF0U
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#define PCI_BUS(bdf) (((bdf) >> 8) & 0xFFU)
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#define PCI_SLOT(bdf) (((bdf) >> 3) & 0x1FU)
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#define PCI_FUNC(bdf) ((bdf) & 0x07U)
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#define LOBYTE(w) ((uint8_t)((w) & 0xffU))
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#define PCI_BUSMAX 0xffU
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#define PCI_SLOTMAX 0x1fU
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#define PCI_BUSMAX 0xFFU
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#define PCI_SLOTMAX 0x1FU
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#define PCI_FUNCMAX 0x7U
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#define MAXBUSES (PCI_BUSMAX + 1U)
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#define MAXSLOTS (PCI_SLOTMAX + 1U)
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#define MAXFUNCS (PCI_FUNCMAX + 1U)
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#define PCIR_VENDOR 0x00U
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#define PCIR_DEVICE 0x02U
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#define PCIR_COMMAND 0x04U
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#define PCIM_CMD_MEMEN 0x0002U
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#define PCIR_REVID 0x08U
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#define PCIR_SUBCLASS 0x0aU
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#define PCIR_CLASS 0x0bU
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#define PCIR_HDRTYPE 0x0eU
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#define PCIR_SUBCLASS 0x0AU
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#define PCIR_CLASS 0x0BU
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#define PCIR_HDRTYPE 0x0EU
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#define PCIM_HDRTYPE_NORMAL 0x00U
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#define PCIM_MFDEV 0x80U
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#define PCIR_BARS 0x10U
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#define PCIR_BAR(x) (PCIR_BARS + ((x) * 4U))
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#define PCIM_BAR_MEM_SPACE 0U
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#define PCIC_BRIDGE 0x06U
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#define PCIS_BRIDGE_HOST 0x00U
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#define PCI_CONFIG_ADDR 0xcf8U
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#define PCI_CONFIG_DATA 0xcfcU
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#define PCI_CONFIG_ADDR 0xCF8U
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#define PCI_CONFIG_DATA 0xCFCU
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#define PCI_CFG_ENABLE 0x80000000U
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void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in, uint16_t vbdf,
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uint32_t offset, uint32_t bytes, uint32_t *val);
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void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in,
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union pci_bdf vbdf, uint32_t offset, uint32_t bytes, uint32_t *val);
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static inline uint8_t
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pci_vdev_read_cfg_u8(struct pci_vdev *vdev, uint32_t offset)
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@ -150,4 +133,19 @@ static inline void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset,
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}
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}
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static inline uint32_t pci_bar_offset(uint32_t idx)
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{
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return 0x10U + (idx << 2U);
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}
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static inline int pci_bar_access(uint32_t offset)
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{
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if ((offset >= pci_bar_offset(0U))
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&& (offset < pci_bar_offset(PCI_BAR_COUNT))) {
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return 1;
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} else {
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return 0;
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}
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}
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#endif /* PCI_PRIV_H_ */
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@ -40,13 +40,17 @@
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static spinlock_t pci_device_lock = { .head = 0, .tail = 0 };
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static uint32_t pci_pdev_calc_address(uint16_t bdf, uint32_t offset)
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static inline uint32_t pci_bar_base(uint32_t bar)
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{
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uint32_t addr = bdf;
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return bar & PCIM_BAR_MEM_BASE;
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}
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addr <<= 8;
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static uint32_t pci_pdev_calc_address(union pci_bdf bdf, uint32_t offset)
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{
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uint32_t addr = (uint32_t)bdf.value;
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addr <<= 8U;
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addr |= (offset | PCI_CFG_ENABLE);
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return addr;
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}
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@ -61,7 +65,7 @@ static uint32_t pci_pdev_read_cfg(struct pci_pdev *pdev,
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addr = pci_pdev_calc_address(pdev->bdf, offset);
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/* Write address to ADDRESS register */
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pio_write(addr, PCI_CONFIG_ADDR, 4);
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pio_write(addr, PCI_CONFIG_ADDR, 4U);
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/* Read result from DATA register */
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switch (bytes) {
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@ -90,7 +94,7 @@ static void pci_pdev_write_cfg(struct pci_pdev *pdev, uint32_t offset,
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addr = pci_pdev_calc_address(pdev->bdf, offset);
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/* Write address to ADDRESS register */
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pio_write(addr, PCI_CONFIG_ADDR, 4);
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pio_write(addr, PCI_CONFIG_ADDR, 4U);
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/* Write value to DATA register */
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switch (bytes) {
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@ -112,7 +116,10 @@ static int vdev_pt_init_validate(struct pci_vdev *vdev)
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uint32_t idx;
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for (idx = 0; idx < (uint32_t)PCI_BAR_COUNT; idx++) {
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if (vdev->bar[idx].type != PCIM_BAR_MEM_32) {
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if ((vdev->bar[idx].base != 0x0UL)
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|| ((vdev->bar[idx].size & 0xFFFUL) != 0x0UL)
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|| ((vdev->bar[idx].type != PCIBAR_MEM32)
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&& (vdev->bar[idx].type != PCIBAR_NONE))) {
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return -EINVAL;
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}
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}
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@ -120,17 +127,6 @@ static int vdev_pt_init_validate(struct pci_vdev *vdev)
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return 0;
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}
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static void vdev_pt_init_bar_registers(struct pci_vdev *vdev)
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{
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uint32_t idx;
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for (idx = 0; idx < (uint32_t)PCI_BAR_COUNT; idx++) {
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/* Initialize the BAR register in config space */
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pci_vdev_write_cfg_u32(vdev, PCIR_BAR(idx),
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PCI_BAR(vdev->bar[idx].base, vdev->bar[idx].type));
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}
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}
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static int vdev_pt_init(struct pci_vdev *vdev)
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{
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int ret;
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@ -138,7 +134,7 @@ static int vdev_pt_init(struct pci_vdev *vdev)
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ret = vdev_pt_init_validate(vdev);
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if (ret != 0) {
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pr_err("virtual bar can only be of type PCIM_BAR_MEM_32!");
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pr_err("Error, invalid bar defined");
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return ret;
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}
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@ -151,10 +147,8 @@ static int vdev_pt_init(struct pci_vdev *vdev)
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HVA2HPA(vm->arch_vm.nworld_eptp), 48U);
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}
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ret = assign_iommu_device(vm->iommu,
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PCI_BUS(vdev->pdev.bdf), LOBYTE(vdev->pdev.bdf));
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vdev_pt_init_bar_registers(vdev);
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ret = assign_iommu_device(vm->iommu, vdev->pdev.bdf.bits.b,
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(uint8_t)(vdev->pdev.bdf.value & 0xFFU));
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return ret;
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}
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@ -164,32 +158,23 @@ static int vdev_pt_deinit(struct pci_vdev *vdev)
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int ret;
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struct vm *vm = vdev->vpci->vm;
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ret = unassign_iommu_device(vm->iommu, PCI_BUS(vdev->pdev.bdf),
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LOBYTE(vdev->pdev.bdf));
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ret = unassign_iommu_device(vm->iommu, vdev->pdev.bdf.bits.b,
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(uint8_t)(vdev->pdev.bdf.value & 0xFFU));
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return ret;
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}
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static int bar_access(uint32_t coff)
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{
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if ((coff >= PCIR_BAR(0U)) && (coff < PCIR_BAR(PCI_BAR_COUNT))) {
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return 1;
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} else {
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return 0;
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}
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}
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static int vdev_pt_cfgread(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t *val)
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{
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/* Assumption: access needed to be aligned on 1/2/4 bytes */
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if ((offset & (bytes - 1)) != 0U) {
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*val = 0xffffffffU;
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if ((offset & (bytes - 1U)) != 0U) {
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*val = 0xFFFFFFFFU;
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return -EINVAL;
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}
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/* PCI BARs is emulated */
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if (bar_access(offset)) {
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if (pci_bar_access(offset)) {
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*val = pci_vdev_read_cfg(vdev, offset, bytes);
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} else {
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*val = pci_pdev_read_cfg(&vdev->pdev, offset, bytes);
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@ -204,11 +189,11 @@ static int vdev_pt_remap_bar(struct pci_vdev *vdev, uint32_t idx,
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int error = 0;
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struct vm *vm = vdev->vpci->vm;
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if (vdev->bar[idx].base != 0) {
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if (vdev->bar[idx].base != 0UL) {
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error = ept_mr_del(vm, (uint64_t *)vm->arch_vm.nworld_eptp,
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vdev->bar[idx].base,
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vdev->bar[idx].size);
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if (error) {
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if (error != 0) {
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return error;
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}
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}
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@ -220,7 +205,7 @@ static int vdev_pt_remap_bar(struct pci_vdev *vdev, uint32_t idx,
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new_base, /*GPA*/
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vdev->bar[idx].size,
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EPT_WR | EPT_RD | EPT_UNCACHED);
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if (error) {
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if (error != 0) {
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return error;
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}
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}
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@ -229,7 +214,7 @@ static int vdev_pt_remap_bar(struct pci_vdev *vdev, uint32_t idx,
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static uint32_t memen(struct pci_vdev *vdev)
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{
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return pci_pdev_read_cfg(&vdev->pdev, PCIR_COMMAND, 2)
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return pci_pdev_read_cfg(&vdev->pdev, PCIR_COMMAND, 2U)
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& PCIM_CMD_MEMEN;
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}
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@ -242,38 +227,41 @@ static void vdev_pt_cfgwrite_bar(struct pci_vdev *vdev, uint32_t offset,
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bool do_map;
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int error;
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idx = (offset - PCIR_BAR(0U)) >> 2U;
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if ((bytes != 4U) || ((offset & 0x3U) != 0U)) {
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return;
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}
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idx = (offset - pci_bar_offset(0U)) >> 2U;
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mask = ~(vdev->bar[idx].size - 1U);
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bar_update_normal = (new_bar_uos != (uint32_t)~0U);
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new_bar = new_bar_uos & mask;
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new_bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32;
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if (PCI_BAR_BASE(new_bar) == vdev->bar[idx].base) {
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if (pci_bar_base(new_bar) == vdev->bar[idx].base) {
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return;
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}
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do_map = (memen(vdev)) && bar_update_normal;
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if (do_map) {
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error = vdev_pt_remap_bar(vdev, idx, PCI_BAR_BASE(new_bar));
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if (error) {
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error = vdev_pt_remap_bar(vdev, idx, pci_bar_base(new_bar));
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if (error != 0) {
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pr_err("vdev_pt_remap_bar failed: %d", idx);
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}
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}
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pci_vdev_write_cfg_u32(vdev, offset, new_bar);
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vdev->bar[idx].base = PCI_BAR_BASE(new_bar);
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vdev->bar[idx].base = pci_bar_base(new_bar);
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}
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static int vdev_pt_cfgwrite(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t val)
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{
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/* Assumption: access needed to be aligned on 1/2/4 bytes */
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if ((offset & (bytes - 1)) != 0U) {
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if ((offset & (bytes - 1U)) != 0U) {
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return -EINVAL;
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}
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/* PCI BARs are emulated */
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if (bar_access(offset)) {
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if (pci_bar_access(offset)) {
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vdev_pt_cfgwrite_bar(vdev, offset, bytes, val);
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} else {
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/* Write directly to physical device's config space */
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@ -286,7 +274,7 @@ static int vdev_pt_cfgwrite(struct pci_vdev *vdev, uint32_t offset,
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struct pci_vdev_ops pci_ops_vdev_pt = {
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.init = vdev_pt_init,
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.deinit = vdev_pt_deinit,
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.cfgwrite = vdev_pt_cfgwrite,
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.cfgread = vdev_pt_cfgread,
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.cfgwrite = vdev_pt_cfgwrite,
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};
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@ -38,7 +38,7 @@
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#include "pci_priv.h"
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static struct pci_vdev *pci_vdev_find(struct vpci *vpci, uint16_t vbdf)
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static struct pci_vdev *pci_vdev_find(struct vpci *vpci, union pci_bdf vbdf)
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{
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struct vpci_vdev_array *vdev_array;
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struct pci_vdev *vdev;
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@ -47,7 +47,7 @@ static struct pci_vdev *pci_vdev_find(struct vpci *vpci, uint16_t vbdf)
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vdev_array = vpci->vm->vm_desc->vpci_vdev_array;
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for (i = 0; i < vdev_array->num_pci_vdev; i++) {
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vdev = &vdev_array->vpci_vdev_list[i];
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if (vdev->vbdf == vbdf) {
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if (vdev->vbdf.value == vbdf.value) {
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return vdev;
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}
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}
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@ -56,7 +56,7 @@ static struct pci_vdev *pci_vdev_find(struct vpci *vpci, uint16_t vbdf)
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}
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/* PCI cfg vm-exit handler */
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void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in, uint16_t vbdf,
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void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in, union pci_bdf vbdf,
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uint32_t offset, uint32_t bytes, uint32_t *val)
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{
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struct pci_vdev *vdev;
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@ -68,7 +68,7 @@ void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in, uint16_t vbdf,
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}
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ret = -EINVAL;
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if (in) {
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if (in == 1U) {
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if ((vdev->ops != NULL) && (vdev->ops->cfgread != NULL)) {
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ret = vdev->ops->cfgread(vdev, offset, bytes, val);
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}
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@ -78,7 +78,7 @@ void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in, uint16_t vbdf,
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}
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}
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if (ret) {
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if (ret != 0) {
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pr_dbg("pci_vdev_cfg_handler failed, ret=%d", ret);
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}
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}
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@ -37,17 +37,17 @@
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static bool is_cfg_addr(uint16_t addr)
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{
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return (addr >= PCI_CONFIG_ADDR) && (addr < (PCI_CONFIG_ADDR + 4));
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return (addr >= PCI_CONFIG_ADDR) && (addr < (PCI_CONFIG_ADDR + 4U));
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}
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static bool is_cfg_data(uint16_t addr)
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{
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return (addr >= PCI_CONFIG_DATA) && (addr < (PCI_CONFIG_DATA + 4));
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return (addr >= PCI_CONFIG_DATA) && (addr < (PCI_CONFIG_DATA + 4U));
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}
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static void pci_cfg_clear_cache(struct pci_addr_info *pi)
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{
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pi->cached_bdf = 0xffffU;
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pi->cached_bdf.value = 0xFFFFU;
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pi->cached_reg = 0U;
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pi->cached_enable = 0U;
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}
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@ -55,33 +55,31 @@ static void pci_cfg_clear_cache(struct pci_addr_info *pi)
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static uint32_t pci_cfg_io_read(__unused struct vm_io_handler *hdlr,
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struct vm *vm, uint16_t addr, size_t bytes)
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{
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uint32_t val = 0xffffffffU;
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uint32_t val = 0xFFFFFFFFU;
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struct vpci *vpci = &vm->vpci;
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struct pci_addr_info *pi = &vpci->addr_info;
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if (is_cfg_addr(addr)) {
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/* TODO: handling the non 4 bytes access */
|
||||
if (bytes == 4U) {
|
||||
val = (PCI_BUS(pi->cached_bdf) << 16)
|
||||
| (PCI_SLOT(pi->cached_bdf) << 11)
|
||||
| (PCI_FUNC(pi->cached_bdf) << 8)
|
||||
| pi->cached_reg;
|
||||
|
||||
val = (uint32_t)pi->cached_bdf.value;
|
||||
val <<= 8U;
|
||||
val |= pi->cached_reg;
|
||||
if (pi->cached_enable) {
|
||||
val |= PCI_CFG_ENABLE;
|
||||
}
|
||||
}
|
||||
} else if (is_cfg_data(addr)) {
|
||||
if (pi->cached_enable) {
|
||||
uint16_t offset = addr - 0xcfc;
|
||||
uint16_t offset = addr - PCI_CONFIG_DATA;
|
||||
|
||||
pci_vdev_cfg_handler(&vm->vpci, 1U, pi->cached_bdf,
|
||||
pci_vdev_cfg_handler(vpci, 1U, pi->cached_bdf,
|
||||
pi->cached_reg + offset, bytes, &val);
|
||||
|
||||
pci_cfg_clear_cache(pi);
|
||||
}
|
||||
} else {
|
||||
val = 0xffffffffU;
|
||||
val = 0xFFFFFFFFU;
|
||||
}
|
||||
|
||||
return val;
|
||||
@ -96,10 +94,9 @@ static void pci_cfg_io_write(__unused struct vm_io_handler *hdlr,
|
||||
if (is_cfg_addr(addr)) {
|
||||
/* TODO: handling the non 4 bytes access */
|
||||
if (bytes == 4U) {
|
||||
pi->cached_bdf = PCI_BDF(
|
||||
((val >> 16) & PCI_BUSMAX),
|
||||
((val >> 11) & PCI_SLOTMAX),
|
||||
((val >> 8) & PCI_FUNCMAX));
|
||||
pi->cached_bdf.bits.b = (val >> 16U) & PCI_BUSMAX;
|
||||
pi->cached_bdf.bits.d = (val >> 11U) & PCI_SLOTMAX;
|
||||
pi->cached_bdf.bits.f = (val >> 8U) & PCI_FUNCMAX;
|
||||
|
||||
pi->cached_reg = val & PCI_REGMAX;
|
||||
pi->cached_enable =
|
||||
@ -107,9 +104,9 @@ static void pci_cfg_io_write(__unused struct vm_io_handler *hdlr,
|
||||
}
|
||||
} else if (is_cfg_data(addr)) {
|
||||
if (pi->cached_enable) {
|
||||
uint16_t offset = addr - 0xcfc;
|
||||
uint16_t offset = addr - PCI_CONFIG_DATA;
|
||||
|
||||
pci_vdev_cfg_handler(&vm->vpci, 0U, pi->cached_bdf,
|
||||
pci_vdev_cfg_handler(vpci, 0U, pi->cached_bdf,
|
||||
pi->cached_reg + offset, bytes, &val);
|
||||
|
||||
pci_cfg_clear_cache(pi);
|
||||
@ -136,9 +133,10 @@ void vpci_init(struct vm *vm)
|
||||
for (i = 0; i < vdev_array->num_pci_vdev; i++) {
|
||||
vdev = &vdev_array->vpci_vdev_list[i];
|
||||
vdev->vpci = vpci;
|
||||
|
||||
if ((vdev->ops != NULL) && (vdev->ops->init != NULL)) {
|
||||
ret = vdev->ops->init(vdev);
|
||||
if (ret) {
|
||||
if (ret != 0) {
|
||||
pr_err("vdev->ops->init failed!");
|
||||
}
|
||||
}
|
||||
@ -161,7 +159,7 @@ void vpci_cleanup(struct vm *vm)
|
||||
vdev = &vdev_array->vpci_vdev_list[i];
|
||||
if ((vdev->ops != NULL) && (vdev->ops->deinit != NULL)) {
|
||||
ret = vdev->ops->deinit(vdev);
|
||||
if (ret) {
|
||||
if (ret != 0) {
|
||||
pr_err("vdev->ops->deinit failed!");
|
||||
}
|
||||
}
|
||||
|
||||
@ -32,14 +32,6 @@
|
||||
|
||||
#define PCI_BAR_COUNT 0x6U
|
||||
#define PCI_REGMAX 0xFFU
|
||||
#define PCIM_BAR_MEM_32 0U
|
||||
#define PCIM_BAR_MEM_64 4U
|
||||
|
||||
#define PCI_BDF(b, d, f) (((b & 0xFFU) << 8) \
|
||||
| ((d & 0x1FU) << 3) | ((f & 0x7U)))
|
||||
|
||||
#define ALIGN_UP(x, y) (((x)+((y)-1))&(~((y)-1U)))
|
||||
#define ALIGN_UP_4K(x) ALIGN_UP(x, 4096)
|
||||
|
||||
struct pci_vdev;
|
||||
struct pci_vdev_ops {
|
||||
@ -54,36 +46,52 @@ struct pci_vdev_ops {
|
||||
uint32_t bytes, uint32_t *val);
|
||||
};
|
||||
|
||||
struct pcibar {
|
||||
union pci_bdf {
|
||||
uint16_t value;
|
||||
|
||||
struct {
|
||||
uint8_t f : 3; /* BITs 0-2 */
|
||||
uint8_t d : 5; /* BITs 3-7 */
|
||||
uint8_t b; /* BITs 8-15 */
|
||||
} bits;
|
||||
};
|
||||
|
||||
enum pci_bar_type {
|
||||
PCIBAR_NONE = 0,
|
||||
PCIBAR_MEM32,
|
||||
PCIBAR_MEM64,
|
||||
};
|
||||
|
||||
struct pci_bar {
|
||||
uint64_t base;
|
||||
uint64_t size;
|
||||
uint8_t type;
|
||||
enum pci_bar_type type;
|
||||
};
|
||||
|
||||
struct pci_pdev {
|
||||
/* The bar info of the physical PCI device. */
|
||||
struct pcibar bar[PCI_BAR_COUNT];
|
||||
struct pci_bar bar[PCI_BAR_COUNT];
|
||||
|
||||
/* The bus/device/function triple of the physical PCI device. */
|
||||
uint16_t bdf;
|
||||
union pci_bdf bdf;
|
||||
};
|
||||
|
||||
struct pci_vdev {
|
||||
struct pci_vdev_ops *ops;
|
||||
struct vpci *vpci;
|
||||
/* The bus/device/function triple of the virtual PCI device. */
|
||||
uint16_t vbdf;
|
||||
union pci_bdf vbdf;
|
||||
|
||||
struct pci_pdev pdev;
|
||||
|
||||
uint8_t cfgdata[PCI_REGMAX + 1U];
|
||||
|
||||
/* The bar info of the virtual PCI device. */
|
||||
struct pcibar bar[PCI_BAR_COUNT];
|
||||
struct pci_bar bar[PCI_BAR_COUNT];
|
||||
};
|
||||
|
||||
struct pci_addr_info {
|
||||
uint16_t cached_bdf;
|
||||
union pci_bdf cached_bdf;
|
||||
uint32_t cached_reg, cached_enable;
|
||||
};
|
||||
|
||||
|
||||
@ -33,39 +33,41 @@ static struct vpci_vdev_array vpci_vdev_array1 = {
|
||||
|
||||
.vpci_vdev_list = {
|
||||
{/*vdev 0: hostbridge */
|
||||
.vbdf = PCI_BDF(0x00U, 0x00U, 0x00U),
|
||||
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
|
||||
.ops = &pci_ops_vdev_hostbridge,
|
||||
.bar = {}, /* don't care for hostbridge */
|
||||
.pdev = {} /* don't care for hostbridge */
|
||||
.bar = {},
|
||||
.pdev = {
|
||||
.bdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
|
||||
}
|
||||
},
|
||||
|
||||
{/*vdev 1*/
|
||||
.vbdf = PCI_BDF(0x00U, 0x01U, 0x00U),
|
||||
.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x0U},
|
||||
.ops = &pci_ops_vdev_pt,
|
||||
.bar = {
|
||||
[0] = {
|
||||
.base = 0UL,
|
||||
.size = ALIGN_UP_4K(0x100UL),
|
||||
.type = PCIM_BAR_MEM_32
|
||||
.size = 0x1000UL,
|
||||
.type = PCIBAR_MEM32
|
||||
},
|
||||
[5] = {
|
||||
.base = 0UL,
|
||||
.size = ALIGN_UP_4K(0x2000UL),
|
||||
.type = PCIM_BAR_MEM_32
|
||||
.size = 0x2000UL,
|
||||
.type = PCIBAR_MEM32
|
||||
},
|
||||
},
|
||||
.pdev = {
|
||||
.bdf = PCI_BDF(0x00U, 0x01U, 0x00U),
|
||||
.bdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x0U},
|
||||
.bar = {
|
||||
[0] = {
|
||||
.base = 0xa9000000UL,
|
||||
.size = 0x100UL,
|
||||
.type = PCIM_BAR_MEM_32
|
||||
.type = PCIBAR_MEM32
|
||||
},
|
||||
[5] = {
|
||||
.base = 0x1a0000000UL,
|
||||
.size = 0x2000UL,
|
||||
.type = PCIM_BAR_MEM_64
|
||||
.type = PCIBAR_MEM64
|
||||
},
|
||||
}
|
||||
}
|
||||
@ -78,39 +80,39 @@ static struct vpci_vdev_array vpci_vdev_array2 = {
|
||||
|
||||
.vpci_vdev_list = {
|
||||
{/*vdev 0: hostbridge*/
|
||||
.vbdf = PCI_BDF(0x00U, 0x00U, 0x00U),
|
||||
.vbdf.bits = {.b = 0x00U, .d = 0x00U, .f = 0x0U},
|
||||
.ops = &pci_ops_vdev_hostbridge,
|
||||
.bar = {}, /* don't care for hostbridge */
|
||||
.pdev = {} /* don't care for hostbridge */
|
||||
},
|
||||
|
||||
{/*vdev 1*/
|
||||
.vbdf = PCI_BDF(0x00U, 0x01U, 0x00U),
|
||||
.vbdf.bits = {.b = 0x00U, .d = 0x01U, .f = 0x0U},
|
||||
.ops = &pci_ops_vdev_pt,
|
||||
.bar = {
|
||||
[0] = {
|
||||
.base = 0UL,
|
||||
.size = ALIGN_UP_4K(0x100UL),
|
||||
.type = PCIM_BAR_MEM_32
|
||||
.size = 0x1000UL,
|
||||
.type = PCIBAR_MEM32
|
||||
},
|
||||
[5] = {
|
||||
.base = 0UL,
|
||||
.size = ALIGN_UP_4K(0x2000UL),
|
||||
.type = PCIM_BAR_MEM_32
|
||||
.size = 0x2000UL,
|
||||
.type = PCIBAR_MEM32
|
||||
},
|
||||
},
|
||||
.pdev = {
|
||||
.bdf = PCI_BDF(0x00U, 0x02U, 0x00U),
|
||||
.bdf.bits = {.b = 0x00U, .d = 0x02U, .f = 0x0U},
|
||||
.bar = {
|
||||
[0] = {
|
||||
.base = 0xa8000000UL,
|
||||
.size = 0x100UL,
|
||||
.type = PCIM_BAR_MEM_32
|
||||
.type = PCIBAR_MEM32
|
||||
},
|
||||
[5] = {
|
||||
.base = 0x1b0000000UL,
|
||||
.size = 0x2000UL,
|
||||
.type = PCIM_BAR_MEM_64
|
||||
.type = PCIBAR_MEM64
|
||||
},
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user