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hv: s3: enable lapic earlier

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After Service VM OS resumes from s3, BSP starts APs asynchronously,
followed by IPIs to APs to resume tsc. This process takes place in
function `host_enter_s3`. While, APs' lapic are not ready to accept IPI
interrupt, so BSP fails to resume tsc.

So enable lapic earlier to make sure that APs are ready.

Tracked-On: #8623
Signed-off-by: Haiwei Li <haiwei.li@intel.com>
This commit is contained in:
Haiwei Li 2023-09-07 06:05:15 +08:00 committed by acrnsi-robot
parent d0fed9901d
commit cdfd35ed3d
1 changed files with 8 additions and 8 deletions
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16
hypervisor/arch/x86/lapic.c
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@ -96,14 +96,6 @@ void early_init_lapic(void)
/* Step2: Enable LAPIC in x2APIC mode */ /* Step2: Enable LAPIC in x2APIC mode */
base.fields.x2APIC_enable = 1U; base.fields.x2APIC_enable = 1U;
msr_write(MSR_IA32_APIC_BASE, base.value); msr_write(MSR_IA32_APIC_BASE, base.value);
}
/**
* @pre pcpu_id < 8U
*/
void init_lapic(uint16_t pcpu_id)
{
per_cpu(lapic_ldr, pcpu_id) = (uint32_t) msr_read(MSR_IA32_EXT_APIC_LDR);
/* Set the mask bits for all the LVT entries by disabling a local APIC software. */ /* Set the mask bits for all the LVT entries by disabling a local APIC software. */
msr_write(MSR_IA32_EXT_APIC_SIVR, 0UL); msr_write(MSR_IA32_EXT_APIC_SIVR, 0UL);
@ -116,6 +108,14 @@ void init_lapic(uint16_t pcpu_id)
clear_lapic_isr(); clear_lapic_isr();
} }
void init_lapic(uint16_t pcpu_id)
{
/* Can not put this to early_init_lapic because logical ID is not
* updated yet.
*/
per_cpu(lapic_ldr, pcpu_id) = (uint32_t) msr_read(MSR_IA32_EXT_APIC_LDR);
}
static void save_lapic(struct lapic_regs *regs) static void save_lapic(struct lapic_regs *regs)
{ {
regs->tpr.v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_TPR); regs->tpr.v = (uint32_t) msr_read(MSR_IA32_EXT_APIC_TPR);