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HV: CAT: add platform specified info for CLOS

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IF CAT is supported, and we want setup initial values to
IA32_Type_MASK_n MSRs, We can define a global structure
platform_clos_array[PLATFORM_CLOS_NUM], it has 2 members:

1.msr_index, the MSR address of IA32_Type_MASK_n
2.clos_masky, the initial valuses

Global varible platform_clos_num is the number of  IA32_Type_MASK_n,
from IA32_Type_MASK_0 to IA32_Type_MASK_<CLOS_MAX_NUM - 1>

Tracked-On: #2462
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
yuhong.tao@intel.com 2019-02-21 05:03:48 +08:00 committed by Eddie Dong
parent ae34fdd843
commit cf524e684d
8 changed files with 93 additions and 0 deletions
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2
hypervisor/Makefile
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@ -140,6 +140,8 @@ C_SRCS += arch/x86/configs/$(CONFIG_BOARD)/ve820.c
C_SRCS += arch/x86/configs/$(CONFIG_BOARD)/pt_dev.c
endif
C_SRCS += arch/x86/configs/$(CONFIG_BOARD)/board.c
C_SRCS += boot/acpi.c
C_SRCS += boot/dmar_parse.c
S_SRCS += arch/x86/idt.S

10
hypervisor/arch/x86/configs/apl-mrb/board.c Normal file
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@ -0,0 +1,10 @@
/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <board.h>
struct platform_clos_info platform_clos_array[0];
uint16_t platform_clos_num = 0;

29
hypervisor/arch/x86/configs/apl-up2/board.c Normal file
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@ -0,0 +1,29 @@
/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <board.h>
#include <msr.h>
struct platform_clos_info platform_clos_array[4] = {
{
.clos_mask = 0xff,
.msr_index = MSR_IA32_L2_MASK_0,
},
{
.clos_mask = 0xff,
.msr_index = MSR_IA32_L2_MASK_1,
},
{
.clos_mask = 0xff,
.msr_index = MSR_IA32_L2_MASK_2,
},
{
.clos_mask = 0xff,
.msr_index = MSR_IA32_L2_MASK_3,
},
};
uint16_t platform_clos_num = (uint16_t)(sizeof(platform_clos_array)/sizeof(struct platform_clos_info));

10
hypervisor/arch/x86/configs/dnv-cb2/board.c Normal file
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@ -0,0 +1,10 @@
/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <board.h>
struct platform_clos_info platform_clos_array[0];
uint16_t platform_clos_num = 0;

10
hypervisor/arch/x86/configs/nuc6cayh/board.c Normal file
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@ -0,0 +1,10 @@
/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <board.h>
struct platform_clos_info platform_clos_array[0];
uint16_t platform_clos_num = 0;

10
hypervisor/arch/x86/configs/nuc7i7bnh/board.c Normal file
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@ -0,0 +1,10 @@
/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <board.h>
struct platform_clos_info platform_clos_array[0];
uint16_t platform_clos_num = 0;

19
hypervisor/include/arch/x86/board.h Normal file
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@ -0,0 +1,19 @@
/*
* Copyright (C) 2019 Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef BOARD_H
#define BOARD_H
#include <types.h>
struct platform_clos_info {
uint32_t clos_mask;
uint32_t msr_index;
};
extern struct platform_clos_info platform_clos_array[];
extern uint16_t platform_clos_num;
#endif /* BOARD_H */

3
hypervisor/include/arch/x86/msr.h
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@ -341,6 +341,9 @@
#define MSR_IA32_PM_CTL1 0x00000DB1U
#define MSR_IA32_THREAD_STALL 0x00000DB2U
#define MSR_IA32_L2_MASK_0 0x00000D10U
#define MSR_IA32_L2_MASK_1 0x00000D11U
#define MSR_IA32_L2_MASK_2 0x00000D12U
#define MSR_IA32_L2_MASK_3 0x00000D13U
#define MSR_IA32_BNDCFGS 0x00000D90U
#define MSR_IA32_EFER 0xC0000080U
#define MSR_IA32_STAR 0xC0000081U