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HV: vmx: convert hexadecimals used in bitops to unsigned

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Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Junjie Mao 2018-06-19 18:32:16 +08:00 committed by lijinxia
parent 41a1035f9b
commit d705970eb2
5 changed files with 457 additions and 457 deletions
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4
hypervisor/arch/x86/ept.c
View File

@ -308,7 +308,7 @@ static int dm_emulate_mmio_pre(struct vcpu *vcpu, uint64_t exit_qual)
return status;
vcpu->req.reqs.mmio_request.value = vcpu->mmio.value;
/* XXX: write access while EPT perm RX -> WP */
if ((exit_qual & 0x38) == 0x28)
if ((exit_qual & 0x38UL) == 0x28UL)
vcpu->req.type = REQ_WP;
}
@ -334,7 +334,7 @@ int ept_violation_vmexit_handler(struct vcpu *vcpu)
exit_qual = vcpu->arch_vcpu.exit_qualification;
/* Specify if read or write operation */
if ((exit_qual & 0x2) != 0U) {
if ((exit_qual & 0x2UL) != 0UL) {
/* Write operation */
mmio->read_write = HV_MEM_IO_WRITE;

30
hypervisor/arch/x86/vmx.c
View File

@ -255,7 +255,7 @@ uint32_t get_cs_access_rights(void)
asm volatile ("movw %%cs, %%ax" : "=a" (sel_value));
asm volatile ("lar %%eax, %%eax" : "=a" (usable_ar) : "a"(sel_value));
usable_ar = usable_ar >> 8;
usable_ar &= 0xf0ff; /* clear bits 11:8 */
usable_ar &= 0xf0ffU; /* clear bits 11:8 */
return usable_ar;
}
@ -620,8 +620,8 @@ static void init_guest_state(struct vcpu *vcpu)
value32 = gdtb.limit;
if (((gdtb.base >> 47) & 0x1) != 0U)
gdtb.base |= 0xffff000000000000ull;
if (((gdtb.base >> 47) & 0x1UL) != 0UL)
gdtb.base |= 0xffff000000000000UL;
base = gdtb.base;
@ -655,8 +655,8 @@ static void init_guest_state(struct vcpu *vcpu)
/* Limit */
limit = idtb.limit;
if (((idtb.base >> 47) & 0x1) != 0U)
idtb.base |= 0xffff000000000000ull;
if (((idtb.base >> 47) & 0x1UL) != 0UL)
idtb.base |= 0xffff000000000000UL;
/* Base */
base = idtb.base;
@ -953,8 +953,8 @@ static void init_host_state(__unused struct vcpu *vcpu)
asm volatile ("sgdt %0"::"m" (gdtb));
value32 = gdtb.limit;
if (((gdtb.base >> 47) & 0x1) != 0U)
gdtb.base |= 0xffff000000000000ull;
if (((gdtb.base >> 47) & 0x1UL) != 0UL)
gdtb.base |= 0xffff000000000000UL;
/* Set up the guest and host GDTB base fields with current GDTB base */
field = VMX_HOST_GDTR_BASE;
@ -963,17 +963,17 @@ static void init_host_state(__unused struct vcpu *vcpu)
/* TODO: Should guest TR point to host TR ? */
trbase = gdtb.base + tr_sel;
if (((trbase >> 47) & 0x1) != 0U)
trbase |= 0xffff000000000000ull;
if (((trbase >> 47) & 0x1UL) != 0UL)
trbase |= 0xffff000000000000UL;
/* SS segment override */
asm volatile ("mov %0,%%rax\n"
".byte 0x36\n"
"movq (%%rax),%%rax\n":"=a" (trbase_lo):"0"(trbase)
);
realtrbase = ((trbase_lo >> 16) & (0x0ffff)) |
(((trbase_lo >> 32) & 0x000000ff) << 16) |
(((trbase_lo >> 56) & 0xff) << 24);
realtrbase = ((trbase_lo >> 16) & (0x0ffffUL)) |
(((trbase_lo >> 32) & 0x000000ffUL) << 16) |
(((trbase_lo >> 56) & 0xffUL) << 24);
/* SS segment override for upper32 bits of base in ia32e mode */
asm volatile ("mov %0,%%rax\n"
@ -989,8 +989,8 @@ static void init_host_state(__unused struct vcpu *vcpu)
/* Obtain the current interrupt descriptor table base */
asm volatile ("sidt %0"::"m" (idtb));
/* base */
if (((idtb.base >> 47) & 0x1) != 0U)
idtb.base |= 0xffff000000000000ull;
if (((idtb.base >> 47) & 0x1UL) != 0UL)
idtb.base |= 0xffff000000000000UL;
field = VMX_HOST_IDTR_BASE;
exec_vmwrite(field, idtb.base);
@ -1210,7 +1210,7 @@ static void init_exec_ctrl(struct vcpu *vcpu)
* TODO: introduce API to make this data driven based
* on VMX_EPT_VPID_CAP
*/
value64 = vm->arch_vm.nworld_eptp | (3 << 3) | 6;
value64 = vm->arch_vm.nworld_eptp | (3UL << 3) | 6UL;
exec_vmwrite64(VMX_EPT_POINTER_FULL, value64);
pr_dbg("VMX_EPT_POINTER: 0x%016llx ", value64);

16
hypervisor/arch/x86/vtd.c
View File

@ -407,10 +407,10 @@ static void dmar_register_hrhd(struct dmar_drhd_rt *dmar_uint)
#endif
/* check capability */
if ((iommu_cap_super_page_val(dmar_uint->cap) & 0x1) == 0)
if ((iommu_cap_super_page_val(dmar_uint->cap) & 0x1UL) == 0)
dev_dbg(ACRN_DBG_IOMMU, "dmar uint doesn't support 2MB page!");
if ((iommu_cap_super_page_val(dmar_uint->cap) & 0x2) == 0)
if ((iommu_cap_super_page_val(dmar_uint->cap) & 0x2UL) == 0)
dev_dbg(ACRN_DBG_IOMMU, "dmar uint doesn't support 1GB page!");
/* when the hardware support snoop control,
@ -675,7 +675,7 @@ static void dmar_fault_msi_write(struct dmar_drhd_rt *dmar_uint,
/* redirection hint: 0
* destination mode: 0
*/
addr_low = 0xFEE00000 | ((lapic_id & 0xFF) << 12);
addr_low = 0xFEE00000U | ((lapic_id & 0xFFU) << 12);
IOMMU_LOCK(dmar_uint);
iommu_write32(dmar_uint, DMAR_FEDATA_REG, data);
@ -722,8 +722,8 @@ static void fault_record_analysis(__unused uint64_t low, uint64_t high)
(DMA_FRCD_UP_T(high) != 0U) ? "Read/Atomic" : "Write",
DMA_FRCD_UP_FR(high),
DMA_FRCD_UP_SID(high) >> 8,
(DMA_FRCD_UP_SID(high) >> 3) & 0x1f,
DMA_FRCD_UP_SID(high) & 0x7,
(DMA_FRCD_UP_SID(high) >> 3) & 0x1fUL,
DMA_FRCD_UP_SID(high) & 0x7UL,
low);
#if DBG_IOMMU
if (iommu_ecap_dt(dmar_uint->ecap))
@ -919,13 +919,13 @@ static int add_iommu_device(struct iommu_domain *domain, uint16_t segment,
dmar_uint = device_to_dmaru(segment, bus, devfun);
if (dmar_uint == NULL) {
pr_err("no dmar unit found for device:0x%x:%x.%x",
bus, devfun >> 3, devfun & 0x7);
bus, devfun >> 3, devfun & 0x7U);
return 1;
}
if (dmar_uint->drhd->ignore) {
dev_dbg(ACRN_DBG_IOMMU, "device is ignored :0x%x:%x.%x",
bus, devfun >> 3, devfun & 0x7);
bus, devfun >> 3, devfun & 0x7U);
return 0;
}
@ -987,7 +987,7 @@ static int add_iommu_device(struct iommu_domain *domain, uint16_t segment,
pr_err("%s: context entry@0x%llx (Lower:%x) ",
__func__, context_entry, context_entry->lower);
pr_err("already present for %x:%x.%x",
bus, devfun >> 3, devfun & 0x7);
bus, devfun >> 3, devfun & 0x7U);
return 1;
}

638
hypervisor/include/arch/x86/vmx.h
View File

@ -8,311 +8,311 @@
#define VMX_H_
/* 16-bit control fields */
#define VMX_VPID 0x00000000
#define VMX_VPID 0x00000000U
/* 16-bit guest-state fields */
#define VMX_GUEST_ES_SEL 0x00000800
#define VMX_GUEST_CS_SEL 0x00000802
#define VMX_GUEST_SS_SEL 0x00000804
#define VMX_GUEST_DS_SEL 0x00000806
#define VMX_GUEST_FS_SEL 0x00000808
#define VMX_GUEST_GS_SEL 0x0000080a
#define VMX_GUEST_LDTR_SEL 0x0000080c
#define VMX_GUEST_TR_SEL 0x0000080e
#define VMX_GUEST_INTR_STATUS 0x00000810
#define VMX_GUEST_ES_SEL 0x00000800U
#define VMX_GUEST_CS_SEL 0x00000802U
#define VMX_GUEST_SS_SEL 0x00000804U
#define VMX_GUEST_DS_SEL 0x00000806U
#define VMX_GUEST_FS_SEL 0x00000808U
#define VMX_GUEST_GS_SEL 0x0000080aU
#define VMX_GUEST_LDTR_SEL 0x0000080cU
#define VMX_GUEST_TR_SEL 0x0000080eU
#define VMX_GUEST_INTR_STATUS 0x00000810U
/* 16-bit host-state fields */
#define VMX_HOST_ES_SEL 0x00000c00
#define VMX_HOST_CS_SEL 0x00000c02
#define VMX_HOST_SS_SEL 0x00000c04
#define VMX_HOST_DS_SEL 0x00000c06
#define VMX_HOST_FS_SEL 0x00000c08
#define VMX_HOST_GS_SEL 0x00000c0a
#define VMX_HOST_TR_SEL 0x00000c0c
#define VMX_HOST_ES_SEL 0x00000c00U
#define VMX_HOST_CS_SEL 0x00000c02U
#define VMX_HOST_SS_SEL 0x00000c04U
#define VMX_HOST_DS_SEL 0x00000c06U
#define VMX_HOST_FS_SEL 0x00000c08U
#define VMX_HOST_GS_SEL 0x00000c0aU
#define VMX_HOST_TR_SEL 0x00000c0cU
/* 64-bit control fields */
#define VMX_IO_BITMAP_A_FULL 0x00002000
#define VMX_IO_BITMAP_A_HIGH 0x00002001
#define VMX_IO_BITMAP_B_FULL 0x00002002
#define VMX_IO_BITMAP_B_HIGH 0x00002003
#define VMX_MSR_BITMAP_FULL 0x00002004
#define VMX_MSR_BITMAP_HIGH 0x00002005
#define VMX_EXIT_MSR_STORE_ADDR_FULL 0x00002006
#define VMX_EXIT_MSR_STORE_ADDR_HIGH 0x00002007
#define VMX_EXIT_MSR_LOAD_ADDR_FULL 0x00002008
#define VMX_EXIT_MSR_LOAD_ADDR_HIGH 0x00002009
#define VMX_ENTRY_MSR_LOAD_ADDR_FULL 0x0000200a
#define VMX_ENTRY_MSR_LOAD_ADDR_HIGH 0x0000200b
#define VMX_EXECUTIVE_VMCS_PTR_FULL 0x0000200c
#define VMX_EXECUTIVE_VMCS_PTR_HIGH 0x0000200d
#define VMX_TSC_OFFSET_FULL 0x00002010
#define VMX_TSC_OFFSET_HIGH 0x00002011
#define VMX_VIRTUAL_APIC_PAGE_ADDR_FULL 0x00002012
#define VMX_VIRTUAL_APIC_PAGE_ADDR_HIGH 0x00002013
#define VMX_APIC_ACCESS_ADDR_FULL 0x00002014
#define VMX_APIC_ACCESS_ADDR_HIGH 0x00002015
#define VMX_EPT_POINTER_FULL 0x0000201A
#define VMX_EPT_POINTER_HIGH 0x0000201B
#define VMX_EOI_EXIT0_FULL 0x0000201C
#define VMX_EOI_EXIT0_HIGH 0x0000201D
#define VMX_EOI_EXIT1_FULL 0x0000201E
#define VMX_EOI_EXIT1_HIGH 0x0000201F
#define VMX_EOI_EXIT2_FULL 0x00002020
#define VMX_EOI_EXIT2_HIGH 0x00002021
#define VMX_EOI_EXIT3_FULL 0x00002022
#define VMX_EOI_EXIT3_HIGH 0x00002023
#define VMX_IO_BITMAP_A_FULL 0x00002000U
#define VMX_IO_BITMAP_A_HIGH 0x00002001U
#define VMX_IO_BITMAP_B_FULL 0x00002002U
#define VMX_IO_BITMAP_B_HIGH 0x00002003U
#define VMX_MSR_BITMAP_FULL 0x00002004U
#define VMX_MSR_BITMAP_HIGH 0x00002005U
#define VMX_EXIT_MSR_STORE_ADDR_FULL 0x00002006U
#define VMX_EXIT_MSR_STORE_ADDR_HIGH 0x00002007U
#define VMX_EXIT_MSR_LOAD_ADDR_FULL 0x00002008U
#define VMX_EXIT_MSR_LOAD_ADDR_HIGH 0x00002009U
#define VMX_ENTRY_MSR_LOAD_ADDR_FULL 0x0000200aU
#define VMX_ENTRY_MSR_LOAD_ADDR_HIGH 0x0000200bU
#define VMX_EXECUTIVE_VMCS_PTR_FULL 0x0000200cU
#define VMX_EXECUTIVE_VMCS_PTR_HIGH 0x0000200dU
#define VMX_TSC_OFFSET_FULL 0x00002010U
#define VMX_TSC_OFFSET_HIGH 0x00002011U
#define VMX_VIRTUAL_APIC_PAGE_ADDR_FULL 0x00002012U
#define VMX_VIRTUAL_APIC_PAGE_ADDR_HIGH 0x00002013U
#define VMX_APIC_ACCESS_ADDR_FULL 0x00002014U
#define VMX_APIC_ACCESS_ADDR_HIGH 0x00002015U
#define VMX_EPT_POINTER_FULL 0x0000201AU
#define VMX_EPT_POINTER_HIGH 0x0000201BU
#define VMX_EOI_EXIT0_FULL 0x0000201CU
#define VMX_EOI_EXIT0_HIGH 0x0000201DU
#define VMX_EOI_EXIT1_FULL 0x0000201EU
#define VMX_EOI_EXIT1_HIGH 0x0000201FU
#define VMX_EOI_EXIT2_FULL 0x00002020U
#define VMX_EOI_EXIT2_HIGH 0x00002021U
#define VMX_EOI_EXIT3_FULL 0x00002022U
#define VMX_EOI_EXIT3_HIGH 0x00002023U
#define VMX_EOI_EXIT(vector) (VMX_EOI_EXIT0_FULL + ((vector) / 64) * 2)
#define VMX_XSS_EXITING_BITMAP_FULL 0x0000202C
#define VMX_XSS_EXITING_BITMAP_HIGH 0x0000202D
#define VMX_XSS_EXITING_BITMAP_FULL 0x0000202CU
#define VMX_XSS_EXITING_BITMAP_HIGH 0x0000202DU
/* 64-bit read-only data fields */
#define VMX_GUEST_PHYSICAL_ADDR_FULL 0x00002400
#define VMX_GUEST_PHYSICAL_ADDR_HIGH 0x00002401
#define VMX_GUEST_PHYSICAL_ADDR_FULL 0x00002400U
#define VMX_GUEST_PHYSICAL_ADDR_HIGH 0x00002401U
/* 64-bit guest-state fields */
#define VMX_VMS_LINK_PTR_FULL 0x00002800
#define VMX_VMS_LINK_PTR_HIGH 0x00002801
#define VMX_GUEST_IA32_DEBUGCTL_FULL 0x00002802
#define VMX_GUEST_IA32_DEBUGCTL_HIGH 0x00002803
#define VMX_GUEST_IA32_PAT_FULL 0x00002804
#define VMX_GUEST_IA32_PAT_HIGH 0x00002805
#define VMX_GUEST_IA32_EFER_FULL 0x00002806
#define VMX_GUEST_IA32_EFER_HIGH 0x00002807
#define VMX_GUEST_IA32_PERF_CTL_FULL 0x00002808
#define VMX_GUEST_IA32_PERF_CTL_HIGH 0x00002809
#define VMX_GUEST_PDPTE0_FULL 0x0000280A
#define VMX_GUEST_PDPTE0_HIGH 0x0000280B
#define VMX_GUEST_PDPTE1_FULL 0x0000280C
#define VMX_GUEST_PDPTE1_HIGH 0x0000280D
#define VMX_GUEST_PDPTE2_FULL 0x0000280E
#define VMX_GUEST_PDPTE2_HIGH 0x0000280F
#define VMX_GUEST_PDPTE3_FULL 0x00002810
#define VMX_GUEST_PDPTE3_HIGH 0x00002811
#define VMX_VMS_LINK_PTR_FULL 0x00002800U
#define VMX_VMS_LINK_PTR_HIGH 0x00002801U
#define VMX_GUEST_IA32_DEBUGCTL_FULL 0x00002802U
#define VMX_GUEST_IA32_DEBUGCTL_HIGH 0x00002803U
#define VMX_GUEST_IA32_PAT_FULL 0x00002804U
#define VMX_GUEST_IA32_PAT_HIGH 0x00002805U
#define VMX_GUEST_IA32_EFER_FULL 0x00002806U
#define VMX_GUEST_IA32_EFER_HIGH 0x00002807U
#define VMX_GUEST_IA32_PERF_CTL_FULL 0x00002808U
#define VMX_GUEST_IA32_PERF_CTL_HIGH 0x00002809U
#define VMX_GUEST_PDPTE0_FULL 0x0000280AU
#define VMX_GUEST_PDPTE0_HIGH 0x0000280BU
#define VMX_GUEST_PDPTE1_FULL 0x0000280CU
#define VMX_GUEST_PDPTE1_HIGH 0x0000280DU
#define VMX_GUEST_PDPTE2_FULL 0x0000280EU
#define VMX_GUEST_PDPTE2_HIGH 0x0000280FU
#define VMX_GUEST_PDPTE3_FULL 0x00002810U
#define VMX_GUEST_PDPTE3_HIGH 0x00002811U
/* 64-bit host-state fields */
#define VMX_HOST_IA32_PAT_FULL 0x00002C00
#define VMX_HOST_IA32_PAT_HIGH 0x00002C01
#define VMX_HOST_IA32_EFER_FULL 0x00002C02
#define VMX_HOST_IA32_EFER_HIGH 0x00002C03
#define VMX_HOST_IA32_PERF_CTL_FULL 0x00002C04
#define VMX_HOST_IA32_PERF_CTL_HIGH 0x00002C05
#define VMX_HOST_IA32_PAT_FULL 0x00002C00U
#define VMX_HOST_IA32_PAT_HIGH 0x00002C01U
#define VMX_HOST_IA32_EFER_FULL 0x00002C02U
#define VMX_HOST_IA32_EFER_HIGH 0x00002C03U
#define VMX_HOST_IA32_PERF_CTL_FULL 0x00002C04U
#define VMX_HOST_IA32_PERF_CTL_HIGH 0x00002C05U
/* 32-bit control fields */
#define VMX_PIN_VM_EXEC_CONTROLS 0x00004000
#define VMX_PROC_VM_EXEC_CONTROLS 0x00004002
#define VMX_EXCEPTION_BITMAP 0x00004004
#define VMX_PF_ERROR_CODE_MASK 0x00004006
#define VMX_PF_ERROR_CODE_MATCH 0x00004008
#define VMX_CR3_TARGET_COUNT 0x0000400a
#define VMX_EXIT_CONTROLS 0x0000400c
#define VMX_EXIT_MSR_STORE_COUNT 0x0000400e
#define VMX_EXIT_MSR_LOAD_COUNT 0x00004010
#define VMX_ENTRY_CONTROLS 0x00004012
#define VMX_ENTRY_MSR_LOAD_COUNT 0x00004014
#define VMX_ENTRY_INT_INFO_FIELD 0x00004016
#define VMX_ENTRY_EXCEPTION_ERROR_CODE 0x00004018
#define VMX_ENTRY_INSTR_LENGTH 0x0000401a
#define VMX_TPR_THRESHOLD 0x0000401c
#define VMX_PROC_VM_EXEC_CONTROLS2 0x0000401E
#define VMX_PLE_GAP 0x00004020
#define VMX_PLE_WINDOW 0x00004022
#define VMX_PIN_VM_EXEC_CONTROLS 0x00004000U
#define VMX_PROC_VM_EXEC_CONTROLS 0x00004002U
#define VMX_EXCEPTION_BITMAP 0x00004004U
#define VMX_PF_ERROR_CODE_MASK 0x00004006U
#define VMX_PF_ERROR_CODE_MATCH 0x00004008U
#define VMX_CR3_TARGET_COUNT 0x0000400aU
#define VMX_EXIT_CONTROLS 0x0000400cU
#define VMX_EXIT_MSR_STORE_COUNT 0x0000400eU
#define VMX_EXIT_MSR_LOAD_COUNT 0x00004010U
#define VMX_ENTRY_CONTROLS 0x00004012U
#define VMX_ENTRY_MSR_LOAD_COUNT 0x00004014U
#define VMX_ENTRY_INT_INFO_FIELD 0x00004016U
#define VMX_ENTRY_EXCEPTION_ERROR_CODE 0x00004018U
#define VMX_ENTRY_INSTR_LENGTH 0x0000401aU
#define VMX_TPR_THRESHOLD 0x0000401cU
#define VMX_PROC_VM_EXEC_CONTROLS2 0x0000401EU
#define VMX_PLE_GAP 0x00004020U
#define VMX_PLE_WINDOW 0x00004022U
/* 32-bit read-only data fields */
#define VMX_INSTR_ERROR 0x00004400
#define VMX_EXIT_REASON 0x00004402
#define VMX_EXIT_INT_INFO 0x00004404
#define VMX_EXIT_INT_ERROR_CODE 0x00004406
#define VMX_IDT_VEC_INFO_FIELD 0x00004408
#define VMX_IDT_VEC_ERROR_CODE 0x0000440a
#define VMX_EXIT_INSTR_LEN 0x0000440c
#define VMX_INSTR_INFO 0x0000440e
#define VMX_INSTR_ERROR 0x00004400U
#define VMX_EXIT_REASON 0x00004402U
#define VMX_EXIT_INT_INFO 0x00004404U
#define VMX_EXIT_INT_ERROR_CODE 0x00004406U
#define VMX_IDT_VEC_INFO_FIELD 0x00004408U
#define VMX_IDT_VEC_ERROR_CODE 0x0000440aU
#define VMX_EXIT_INSTR_LEN 0x0000440cU
#define VMX_INSTR_INFO 0x0000440eU
/* 32-bit guest-state fields */
#define VMX_GUEST_ES_LIMIT 0x00004800
#define VMX_GUEST_CS_LIMIT 0x00004802
#define VMX_GUEST_SS_LIMIT 0x00004804
#define VMX_GUEST_DS_LIMIT 0x00004806
#define VMX_GUEST_FS_LIMIT 0x00004808
#define VMX_GUEST_GS_LIMIT 0x0000480a
#define VMX_GUEST_LDTR_LIMIT 0x0000480c
#define VMX_GUEST_TR_LIMIT 0x0000480e
#define VMX_GUEST_GDTR_LIMIT 0x00004810
#define VMX_GUEST_IDTR_LIMIT 0x00004812
#define VMX_GUEST_ES_ATTR 0x00004814
#define VMX_GUEST_CS_ATTR 0x00004816
#define VMX_GUEST_SS_ATTR 0x00004818
#define VMX_GUEST_DS_ATTR 0x0000481a
#define VMX_GUEST_FS_ATTR 0x0000481c
#define VMX_GUEST_GS_ATTR 0x0000481e
#define VMX_GUEST_LDTR_ATTR 0x00004820
#define VMX_GUEST_TR_ATTR 0x00004822
#define VMX_GUEST_INTERRUPTIBILITY_INFO 0x00004824
#define VMX_GUEST_ACTIVITY_STATE 0x00004826
#define VMX_GUEST_SMBASE 0x00004828
#define VMX_GUEST_IA32_SYSENTER_CS 0x0000482a
#define VMX_GUEST_TIMER 0x0000482E
#define VMX_GUEST_ES_LIMIT 0x00004800U
#define VMX_GUEST_CS_LIMIT 0x00004802U
#define VMX_GUEST_SS_LIMIT 0x00004804U
#define VMX_GUEST_DS_LIMIT 0x00004806U
#define VMX_GUEST_FS_LIMIT 0x00004808U
#define VMX_GUEST_GS_LIMIT 0x0000480aU
#define VMX_GUEST_LDTR_LIMIT 0x0000480cU
#define VMX_GUEST_TR_LIMIT 0x0000480eU
#define VMX_GUEST_GDTR_LIMIT 0x00004810U
#define VMX_GUEST_IDTR_LIMIT 0x00004812U
#define VMX_GUEST_ES_ATTR 0x00004814U
#define VMX_GUEST_CS_ATTR 0x00004816U
#define VMX_GUEST_SS_ATTR 0x00004818U
#define VMX_GUEST_DS_ATTR 0x0000481aU
#define VMX_GUEST_FS_ATTR 0x0000481cU
#define VMX_GUEST_GS_ATTR 0x0000481eU
#define VMX_GUEST_LDTR_ATTR 0x00004820U
#define VMX_GUEST_TR_ATTR 0x00004822U
#define VMX_GUEST_INTERRUPTIBILITY_INFO 0x00004824U
#define VMX_GUEST_ACTIVITY_STATE 0x00004826U
#define VMX_GUEST_SMBASE 0x00004828U
#define VMX_GUEST_IA32_SYSENTER_CS 0x0000482aU
#define VMX_GUEST_TIMER 0x0000482EU
/* 32-bit host-state fields */
#define VMX_HOST_IA32_SYSENTER_CS 0x00004c00
#define VMX_HOST_IA32_SYSENTER_CS 0x00004c00U
/* natural-width control fields */
#define VMX_CR0_MASK 0x00006000
#define VMX_CR4_MASK 0x00006002
#define VMX_CR0_READ_SHADOW 0x00006004
#define VMX_CR4_READ_SHADOW 0x00006006
#define VMX_CR3_TARGET_0 0x00006008
#define VMX_CR3_TARGET_1 0x0000600a
#define VMX_CR3_TARGET_2 0x0000600c
#define VMX_CR3_TARGET_3 0x0000600e
#define VMX_CR0_MASK 0x00006000U
#define VMX_CR4_MASK 0x00006002U
#define VMX_CR0_READ_SHADOW 0x00006004U
#define VMX_CR4_READ_SHADOW 0x00006006U
#define VMX_CR3_TARGET_0 0x00006008U
#define VMX_CR3_TARGET_1 0x0000600aU
#define VMX_CR3_TARGET_2 0x0000600cU
#define VMX_CR3_TARGET_3 0x0000600eU
/* natural-width read-only data fields */
#define VMX_EXIT_QUALIFICATION 0x00006400
#define VMX_IO_RCX 0x00006402
#define VMX_IO_RDI 0x00006406
#define VMX_GUEST_LINEAR_ADDR 0x0000640a
#define VMX_EXIT_QUALIFICATION 0x00006400U
#define VMX_IO_RCX 0x00006402U
#define VMX_IO_RDI 0x00006406U
#define VMX_GUEST_LINEAR_ADDR 0x0000640aU
/* natural-width guest-state fields */
#define VMX_GUEST_CR0 0x00006800
#define VMX_GUEST_CR3 0x00006802
#define VMX_GUEST_CR4 0x00006804
#define VMX_GUEST_ES_BASE 0x00006806
#define VMX_GUEST_CS_BASE 0x00006808
#define VMX_GUEST_SS_BASE 0x0000680a
#define VMX_GUEST_DS_BASE 0x0000680c
#define VMX_GUEST_FS_BASE 0x0000680e
#define VMX_GUEST_GS_BASE 0x00006810
#define VMX_GUEST_LDTR_BASE 0x00006812
#define VMX_GUEST_TR_BASE 0x00006814
#define VMX_GUEST_GDTR_BASE 0x00006816
#define VMX_GUEST_IDTR_BASE 0x00006818
#define VMX_GUEST_DR7 0x0000681a
#define VMX_GUEST_RSP 0x0000681c
#define VMX_GUEST_RIP 0x0000681e
#define VMX_GUEST_RFLAGS 0x00006820
#define VMX_GUEST_PENDING_DEBUG_EXCEPT 0x00006822
#define VMX_GUEST_IA32_SYSENTER_ESP 0x00006824
#define VMX_GUEST_IA32_SYSENTER_EIP 0x00006826
#define VMX_GUEST_CR0 0x00006800U
#define VMX_GUEST_CR3 0x00006802U
#define VMX_GUEST_CR4 0x00006804U
#define VMX_GUEST_ES_BASE 0x00006806U
#define VMX_GUEST_CS_BASE 0x00006808U
#define VMX_GUEST_SS_BASE 0x0000680aU
#define VMX_GUEST_DS_BASE 0x0000680cU
#define VMX_GUEST_FS_BASE 0x0000680eU
#define VMX_GUEST_GS_BASE 0x00006810U
#define VMX_GUEST_LDTR_BASE 0x00006812U
#define VMX_GUEST_TR_BASE 0x00006814U
#define VMX_GUEST_GDTR_BASE 0x00006816U
#define VMX_GUEST_IDTR_BASE 0x00006818U
#define VMX_GUEST_DR7 0x0000681aU
#define VMX_GUEST_RSP 0x0000681cU
#define VMX_GUEST_RIP 0x0000681eU
#define VMX_GUEST_RFLAGS 0x00006820U
#define VMX_GUEST_PENDING_DEBUG_EXCEPT 0x00006822U
#define VMX_GUEST_IA32_SYSENTER_ESP 0x00006824U
#define VMX_GUEST_IA32_SYSENTER_EIP 0x00006826U
/* natural-width host-state fields */
#define VMX_HOST_CR0 0x00006c00
#define VMX_HOST_CR3 0x00006c02
#define VMX_HOST_CR4 0x00006c04
#define VMX_HOST_FS_BASE 0x00006c06
#define VMX_HOST_GS_BASE 0x00006c08
#define VMX_HOST_TR_BASE 0x00006c0a
#define VMX_HOST_GDTR_BASE 0x00006c0c
#define VMX_HOST_IDTR_BASE 0x00006c0e
#define VMX_HOST_IA32_SYSENTER_ESP 0x00006c10
#define VMX_HOST_IA32_SYSENTER_EIP 0x00006c12
#define VMX_HOST_RSP 0x00006c14
#define VMX_HOST_RIP 0x00006c16
#define VMX_HOST_CR0 0x00006c00U
#define VMX_HOST_CR3 0x00006c02U
#define VMX_HOST_CR4 0x00006c04U
#define VMX_HOST_FS_BASE 0x00006c06U
#define VMX_HOST_GS_BASE 0x00006c08U
#define VMX_HOST_TR_BASE 0x00006c0aU
#define VMX_HOST_GDTR_BASE 0x00006c0cU
#define VMX_HOST_IDTR_BASE 0x00006c0eU
#define VMX_HOST_IA32_SYSENTER_ESP 0x00006c10U
#define VMX_HOST_IA32_SYSENTER_EIP 0x00006c12U
#define VMX_HOST_RSP 0x00006c14U
#define VMX_HOST_RIP 0x00006c16U
/*
* Basic VM exit reasons
*/
#define VMX_EXIT_REASON_EXCEPTION_OR_NMI 0x00000000
#define VMX_EXIT_REASON_EXTERNAL_INTERRUPT 0x00000001
#define VMX_EXIT_REASON_TRIPLE_FAULT 0x00000002
#define VMX_EXIT_REASON_INIT_SIGNAL 0x00000003
#define VMX_EXIT_REASON_STARTUP_IPI 0x00000004
#define VMX_EXIT_REASON_IO_SMI 0x00000005
#define VMX_EXIT_REASON_OTHER_SMI 0x00000006
#define VMX_EXIT_REASON_INTERRUPT_WINDOW 0x00000007
#define VMX_EXIT_REASON_NMI_WINDOW 0x00000008
#define VMX_EXIT_REASON_TASK_SWITCH 0x00000009
#define VMX_EXIT_REASON_CPUID 0x0000000A
#define VMX_EXIT_REASON_GETSEC 0x0000000B
#define VMX_EXIT_REASON_HLT 0x0000000C
#define VMX_EXIT_REASON_INVD 0x0000000D
#define VMX_EXIT_REASON_INVLPG 0x0000000E
#define VMX_EXIT_REASON_RDPMC 0x0000000F
#define VMX_EXIT_REASON_RDTSC 0x00000010
#define VMX_EXIT_REASON_RSM 0x00000011
#define VMX_EXIT_REASON_VMCALL 0x00000012
#define VMX_EXIT_REASON_VMCLEAR 0x00000013
#define VMX_EXIT_REASON_VMLAUNCH 0x00000014
#define VMX_EXIT_REASON_VMPTRLD 0x00000015
#define VMX_EXIT_REASON_VMPTRST 0x00000016
#define VMX_EXIT_REASON_VMREAD 0x00000017
#define VMX_EXIT_REASON_VMRESUME 0x00000018
#define VMX_EXIT_REASON_VMWRITE 0x00000019
#define VMX_EXIT_REASON_VMXOFF 0x0000001A
#define VMX_EXIT_REASON_VMXON 0x0000001B
#define VMX_EXIT_REASON_CR_ACCESS 0x0000001C
#define VMX_EXIT_REASON_DR_ACCESS 0x0000001D
#define VMX_EXIT_REASON_IO_INSTRUCTION 0x0000001E
#define VMX_EXIT_REASON_RDMSR 0x0000001F
#define VMX_EXIT_REASON_WRMSR 0x00000020
#define VMX_EXIT_REASON_ENTRY_FAILURE_INVALID_GUEST_STATE 0x00000021
#define VMX_EXIT_REASON_ENTRY_FAILURE_MSR_LOADING 0x00000022
#define VMX_EXIT_REASON_EXCEPTION_OR_NMI 0x00000000U
#define VMX_EXIT_REASON_EXTERNAL_INTERRUPT 0x00000001U
#define VMX_EXIT_REASON_TRIPLE_FAULT 0x00000002U
#define VMX_EXIT_REASON_INIT_SIGNAL 0x00000003U
#define VMX_EXIT_REASON_STARTUP_IPI 0x00000004U
#define VMX_EXIT_REASON_IO_SMI 0x00000005U
#define VMX_EXIT_REASON_OTHER_SMI 0x00000006U
#define VMX_EXIT_REASON_INTERRUPT_WINDOW 0x00000007U
#define VMX_EXIT_REASON_NMI_WINDOW 0x00000008U
#define VMX_EXIT_REASON_TASK_SWITCH 0x00000009U
#define VMX_EXIT_REASON_CPUID 0x0000000AU
#define VMX_EXIT_REASON_GETSEC 0x0000000BU
#define VMX_EXIT_REASON_HLT 0x0000000CU
#define VMX_EXIT_REASON_INVD 0x0000000DU
#define VMX_EXIT_REASON_INVLPG 0x0000000EU
#define VMX_EXIT_REASON_RDPMC 0x0000000FU
#define VMX_EXIT_REASON_RDTSC 0x00000010U
#define VMX_EXIT_REASON_RSM 0x00000011U
#define VMX_EXIT_REASON_VMCALL 0x00000012U
#define VMX_EXIT_REASON_VMCLEAR 0x00000013U
#define VMX_EXIT_REASON_VMLAUNCH 0x00000014U
#define VMX_EXIT_REASON_VMPTRLD 0x00000015U
#define VMX_EXIT_REASON_VMPTRST 0x00000016U
#define VMX_EXIT_REASON_VMREAD 0x00000017U
#define VMX_EXIT_REASON_VMRESUME 0x00000018U
#define VMX_EXIT_REASON_VMWRITE 0x00000019U
#define VMX_EXIT_REASON_VMXOFF 0x0000001AU
#define VMX_EXIT_REASON_VMXON 0x0000001BU
#define VMX_EXIT_REASON_CR_ACCESS 0x0000001CU
#define VMX_EXIT_REASON_DR_ACCESS 0x0000001DU
#define VMX_EXIT_REASON_IO_INSTRUCTION 0x0000001EU
#define VMX_EXIT_REASON_RDMSR 0x0000001FU
#define VMX_EXIT_REASON_WRMSR 0x00000020U
#define VMX_EXIT_REASON_ENTRY_FAILURE_INVALID_GUEST_STATE 0x00000021U
#define VMX_EXIT_REASON_ENTRY_FAILURE_MSR_LOADING 0x00000022U
/* entry 0x23 (35) is missing */
#define VMX_EXIT_REASON_MWAIT 0x00000024
#define VMX_EXIT_REASON_MONITOR_TRAP 0x00000025
#define VMX_EXIT_REASON_MWAIT 0x00000024U
#define VMX_EXIT_REASON_MONITOR_TRAP 0x00000025U
/* entry 0x26 (38) is missing */
#define VMX_EXIT_REASON_MONITOR 0x00000027
#define VMX_EXIT_REASON_PAUSE 0x00000028
#define VMX_EXIT_REASON_ENTRY_FAILURE_MACHINE_CHECK 0x00000029
#define VMX_EXIT_REASON_MONITOR 0x00000027U
#define VMX_EXIT_REASON_PAUSE 0x00000028U
#define VMX_EXIT_REASON_ENTRY_FAILURE_MACHINE_CHECK 0x00000029U
/* entry 0x2A (42) is missing */
#define VMX_EXIT_REASON_TPR_BELOW_THRESHOLD 0x0000002B
#define VMX_EXIT_REASON_APIC_ACCESS 0x0000002C
#define VMX_EXIT_REASON_VIRTUALIZED_EOI 0x0000002D
#define VMX_EXIT_REASON_GDTR_IDTR_ACCESS 0x0000002E
#define VMX_EXIT_REASON_LDTR_TR_ACCESS 0x0000002F
#define VMX_EXIT_REASON_EPT_VIOLATION 0x00000030
#define VMX_EXIT_REASON_EPT_MISCONFIGURATION 0x00000031
#define VMX_EXIT_REASON_INVEPT 0x00000032
#define VMX_EXIT_REASON_RDTSCP 0x00000033
#define VMX_EXIT_REASON_VMX_PREEMPTION_TIMER_EXPIRED 0x00000034
#define VMX_EXIT_REASON_INVVPID 0x00000035
#define VMX_EXIT_REASON_WBINVD 0x00000036
#define VMX_EXIT_REASON_XSETBV 0x00000037
#define VMX_EXIT_REASON_APIC_WRITE 0x00000038
#define VMX_EXIT_REASON_TPR_BELOW_THRESHOLD 0x0000002BU
#define VMX_EXIT_REASON_APIC_ACCESS 0x0000002CU
#define VMX_EXIT_REASON_VIRTUALIZED_EOI 0x0000002DU
#define VMX_EXIT_REASON_GDTR_IDTR_ACCESS 0x0000002EU
#define VMX_EXIT_REASON_LDTR_TR_ACCESS 0x0000002FU
#define VMX_EXIT_REASON_EPT_VIOLATION 0x00000030U
#define VMX_EXIT_REASON_EPT_MISCONFIGURATION 0x00000031U
#define VMX_EXIT_REASON_INVEPT 0x00000032U
#define VMX_EXIT_REASON_RDTSCP 0x00000033U
#define VMX_EXIT_REASON_VMX_PREEMPTION_TIMER_EXPIRED 0x00000034U
#define VMX_EXIT_REASON_INVVPID 0x00000035U
#define VMX_EXIT_REASON_WBINVD 0x00000036U
#define VMX_EXIT_REASON_XSETBV 0x00000037U
#define VMX_EXIT_REASON_APIC_WRITE 0x00000038U
/* VMX execution control bits (pin based) */
#define VMX_PINBASED_CTLS_IRQ_EXIT (1<<0)
#define VMX_PINBASED_CTLS_NMI_EXIT (1<<3)
#define VMX_PINBASED_CTLS_VIRT_NMI (1<<5)
#define VMX_PINBASED_CTLS_ENABLE_PTMR (1<<6)
#define VMX_PINBASED_CTLS_POST_IRQ (1<<7)
#define VMX_PINBASED_CTLS_IRQ_EXIT (1U<<0)
#define VMX_PINBASED_CTLS_NMI_EXIT (1U<<3)
#define VMX_PINBASED_CTLS_VIRT_NMI (1U<<5)
#define VMX_PINBASED_CTLS_ENABLE_PTMR (1U<<6)
#define VMX_PINBASED_CTLS_POST_IRQ (1U<<7)
/* VMX execution control bits (processor based) */
#define VMX_PROCBASED_CTLS_IRQ_WIN (1<<2)
#define VMX_PROCBASED_CTLS_TSC_OFF (1<<3)
#define VMX_PROCBASED_CTLS_HLT (1<<7)
#define VMX_PROCBASED_CTLS_INVLPG (1<<9)
#define VMX_PROCBASED_CTLS_MWAIT (1<<10)
#define VMX_PROCBASED_CTLS_RDPMC (1<<11)
#define VMX_PROCBASED_CTLS_RDTSC (1<<12)
#define VMX_PROCBASED_CTLS_CR3_LOAD (1<<15)
#define VMX_PROCBASED_CTLS_CR3_STORE (1<<16)
#define VMX_PROCBASED_CTLS_CR8_LOAD (1<<19)
#define VMX_PROCBASED_CTLS_CR8_STORE (1<<20)
#define VMX_PROCBASED_CTLS_TPR_SHADOW (1<<21)
#define VMX_PROCBASED_CTLS_NMI_WINEXIT (1<<22)
#define VMX_PROCBASED_CTLS_MOV_DR (1<<23)
#define VMX_PROCBASED_CTLS_UNCOND_IO (1<<24)
#define VMX_PROCBASED_CTLS_IO_BITMAP (1<<25)
#define VMX_PROCBASED_CTLS_MON_TRAP (1<<27)
#define VMX_PROCBASED_CTLS_MSR_BITMAP (1<<28)
#define VMX_PROCBASED_CTLS_MONITOR (1<<29)
#define VMX_PROCBASED_CTLS_PAUSE (1<<30)
#define VMX_PROCBASED_CTLS_SECONDARY (1<<31)
#define VMX_PROCBASED_CTLS2_VAPIC (1<<0)
#define VMX_PROCBASED_CTLS2_EPT (1<<1)
#define VMX_PROCBASED_CTLS2_DESC_TABLE (1<<2)
#define VMX_PROCBASED_CTLS2_RDTSCP (1<<3)
#define VMX_PROCBASED_CTLS2_VX2APIC (1<<4)
#define VMX_PROCBASED_CTLS2_VPID (1<<5)
#define VMX_PROCBASED_CTLS2_WBINVD (1<<6)
#define VMX_PROCBASED_CTLS2_UNRESTRICT (1<<7)
#define VMX_PROCBASED_CTLS2_VAPIC_REGS (1<<8)
#define VMX_PROCBASED_CTLS2_VIRQ (1<<9)
#define VMX_PROCBASED_CTLS2_PAUSE_LOOP (1<<10)
#define VMX_PROCBASED_CTLS2_RDRAND (1<<11)
#define VMX_PROCBASED_CTLS2_INVPCID (1<<12)
#define VMX_PROCBASED_CTLS2_VM_FUNCS (1<<13)
#define VMX_PROCBASED_CTLS2_VMCS_SHADW (1<<14)
#define VMX_PROCBASED_CTLS2_RDSEED (1<<16)
#define VMX_PROCBASED_CTLS2_EPT_VE (1<<18)
#define VMX_PROCBASED_CTLS2_XSVE_XRSTR (1<<20)
#define VMX_PROCBASED_CTLS_IRQ_WIN (1U<<2)
#define VMX_PROCBASED_CTLS_TSC_OFF (1U<<3)
#define VMX_PROCBASED_CTLS_HLT (1U<<7)
#define VMX_PROCBASED_CTLS_INVLPG (1U<<9)
#define VMX_PROCBASED_CTLS_MWAIT (1U<<10)
#define VMX_PROCBASED_CTLS_RDPMC (1U<<11)
#define VMX_PROCBASED_CTLS_RDTSC (1U<<12)
#define VMX_PROCBASED_CTLS_CR3_LOAD (1U<<15)
#define VMX_PROCBASED_CTLS_CR3_STORE (1U<<16)
#define VMX_PROCBASED_CTLS_CR8_LOAD (1U<<19)
#define VMX_PROCBASED_CTLS_CR8_STORE (1U<<20)
#define VMX_PROCBASED_CTLS_TPR_SHADOW (1U<<21)
#define VMX_PROCBASED_CTLS_NMI_WINEXIT (1U<<22)
#define VMX_PROCBASED_CTLS_MOV_DR (1U<<23)
#define VMX_PROCBASED_CTLS_UNCOND_IO (1U<<24)
#define VMX_PROCBASED_CTLS_IO_BITMAP (1U<<25)
#define VMX_PROCBASED_CTLS_MON_TRAP (1U<<27)
#define VMX_PROCBASED_CTLS_MSR_BITMAP (1U<<28)
#define VMX_PROCBASED_CTLS_MONITOR (1U<<29)
#define VMX_PROCBASED_CTLS_PAUSE (1U<<30)
#define VMX_PROCBASED_CTLS_SECONDARY (1U<<31)
#define VMX_PROCBASED_CTLS2_VAPIC (1U<<0)
#define VMX_PROCBASED_CTLS2_EPT (1U<<1)
#define VMX_PROCBASED_CTLS2_DESC_TABLE (1U<<2)
#define VMX_PROCBASED_CTLS2_RDTSCP (1U<<3)
#define VMX_PROCBASED_CTLS2_VX2APIC (1U<<4)
#define VMX_PROCBASED_CTLS2_VPID (1U<<5)
#define VMX_PROCBASED_CTLS2_WBINVD (1U<<6)
#define VMX_PROCBASED_CTLS2_UNRESTRICT (1U<<7)
#define VMX_PROCBASED_CTLS2_VAPIC_REGS (1U<<8)
#define VMX_PROCBASED_CTLS2_VIRQ (1U<<9)
#define VMX_PROCBASED_CTLS2_PAUSE_LOOP (1U<<10)
#define VMX_PROCBASED_CTLS2_RDRAND (1U<<11)
#define VMX_PROCBASED_CTLS2_INVPCID (1U<<12)
#define VMX_PROCBASED_CTLS2_VM_FUNCS (1U<<13)
#define VMX_PROCBASED_CTLS2_VMCS_SHADW (1U<<14)
#define VMX_PROCBASED_CTLS2_RDSEED (1U<<16)
#define VMX_PROCBASED_CTLS2_EPT_VE (1U<<18)
#define VMX_PROCBASED_CTLS2_XSVE_XRSTR (1U<<20)
/* MSR_IA32_VMX_EPT_VPID_CAP: EPT and VPID capability bits */
#define VMX_EPT_EXECUTE_ONLY (1 << 0)
#define VMX_EPT_PAGE_WALK_4 (1 << 6)
#define VMX_EPT_PAGE_WALK_5 (1 << 7)
#define VMX_EPTP_UC (1 << 8)
#define VMX_EPTP_WB (1 << 14)
#define VMX_EPT_2MB_PAGE (1 << 16)
#define VMX_EPT_1GB_PAGE (1 << 17)
#define VMX_EPT_INVEPT (1 << 20)
#define VMX_EPT_AD (1 << 21)
#define VMX_EPT_INVEPT_SINGLE_CONTEXT (1 << 25)
#define VMX_EPT_INVEPT_GLOBAL_CONTEXT (1 << 26)
#define VMX_EPT_EXECUTE_ONLY (1U << 0)
#define VMX_EPT_PAGE_WALK_4 (1U << 6)
#define VMX_EPT_PAGE_WALK_5 (1U << 7)
#define VMX_EPTP_UC (1U << 8)
#define VMX_EPTP_WB (1U << 14)
#define VMX_EPT_2MB_PAGE (1U << 16)
#define VMX_EPT_1GB_PAGE (1U << 17)
#define VMX_EPT_INVEPT (1U << 20)
#define VMX_EPT_AD (1U << 21)
#define VMX_EPT_INVEPT_SINGLE_CONTEXT (1U << 25)
#define VMX_EPT_INVEPT_GLOBAL_CONTEXT (1U << 26)
#define VMX_MIN_NR_VPID 1
#define VMX_MAX_NR_VPID (1 << 5)
@ -322,49 +322,49 @@
#define VMX_VPID_TYPE_ALL_CONTEXT 2
#define VMX_VPID_TYPE_SINGLE_NON_GLOBAL 3
#define VMX_VPID_INVVPID (1 << 0) /* (32 - 32) */
#define VMX_VPID_INVVPID_INDIVIDUAL_ADDR (1 << 8) /* (40 - 32) */
#define VMX_VPID_INVVPID_SINGLE_CONTEXT (1 << 9) /* (41 - 32) */
#define VMX_VPID_INVVPID_GLOBAL_CONTEXT (1 << 10) /* (42 - 32) */
#define VMX_VPID_INVVPID_SINGLE_NON_GLOBAL (1 << 11) /* (43 - 32) */
#define VMX_VPID_INVVPID (1U << 0) /* (32 - 32) */
#define VMX_VPID_INVVPID_INDIVIDUAL_ADDR (1U << 8) /* (40 - 32) */
#define VMX_VPID_INVVPID_SINGLE_CONTEXT (1U << 9) /* (41 - 32) */
#define VMX_VPID_INVVPID_GLOBAL_CONTEXT (1U << 10) /* (42 - 32) */
#define VMX_VPID_INVVPID_SINGLE_NON_GLOBAL (1U << 11) /* (43 - 32) */
#define VMX_EPT_MT_EPTE_SHIFT 3
#define VMX_EPTP_PWL_MASK 0x38
#define VMX_EPTP_PWL_4 0x18
#define VMX_EPTP_PWL_5 0x20
#define VMX_EPTP_AD_ENABLE_BIT (1 << 6)
#define VMX_EPTP_MT_MASK 0x7
#define VMX_EPTP_MT_WB 0x6
#define VMX_EPTP_MT_UC 0x0
#define VMX_EPTP_PWL_MASK 0x38UL
#define VMX_EPTP_PWL_4 0x18UL
#define VMX_EPTP_PWL_5 0x20UL
#define VMX_EPTP_AD_ENABLE_BIT (1UL << 6)
#define VMX_EPTP_MT_MASK 0x7UL
#define VMX_EPTP_MT_WB 0x6UL
#define VMX_EPTP_MT_UC 0x0UL
/* VMX exit control bits */
#define VMX_EXIT_CTLS_SAVE_DBG (1<<2)
#define VMX_EXIT_CTLS_HOST_ADDR64 (1<<9)
#define VMX_EXIT_CTLS_LOAD_PERF (1<<12)
#define VMX_EXIT_CTLS_ACK_IRQ (1<<15)
#define VMX_EXIT_CTLS_SAVE_PAT (1<<18)
#define VMX_EXIT_CTLS_LOAD_PAT (1<<19)
#define VMX_EXIT_CTLS_SAVE_EFER (1<<20)
#define VMX_EXIT_CTLS_LOAD_EFER (1<<21)
#define VMX_EXIT_CTLS_SAVE_PTMR (1<<22)
#define VMX_EXIT_CTLS_SAVE_DBG (1U<<2)
#define VMX_EXIT_CTLS_HOST_ADDR64 (1U<<9)
#define VMX_EXIT_CTLS_LOAD_PERF (1U<<12)
#define VMX_EXIT_CTLS_ACK_IRQ (1U<<15)
#define VMX_EXIT_CTLS_SAVE_PAT (1U<<18)
#define VMX_EXIT_CTLS_LOAD_PAT (1U<<19)
#define VMX_EXIT_CTLS_SAVE_EFER (1U<<20)
#define VMX_EXIT_CTLS_LOAD_EFER (1U<<21)
#define VMX_EXIT_CTLS_SAVE_PTMR (1U<<22)
/* VMX entry control bits */
#define VMX_ENTRY_CTLS_LOAD_DBG (1<<2)
#define VMX_ENTRY_CTLS_IA32E_MODE (1<<9)
#define VMX_ENTRY_CTLS_ENTRY_SMM (1<<10)
#define VMX_ENTRY_CTLS_DEACT_DUAL (1<<11)
#define VMX_ENTRY_CTLS_LOAD_PERF (1<<13)
#define VMX_ENTRY_CTLS_LOAD_PAT (1<<14)
#define VMX_ENTRY_CTLS_LOAD_EFER (1<<15)
#define VMX_ENTRY_CTLS_LOAD_DBG (1U<<2)
#define VMX_ENTRY_CTLS_IA32E_MODE (1U<<9)
#define VMX_ENTRY_CTLS_ENTRY_SMM (1U<<10)
#define VMX_ENTRY_CTLS_DEACT_DUAL (1U<<11)
#define VMX_ENTRY_CTLS_LOAD_PERF (1U<<13)
#define VMX_ENTRY_CTLS_LOAD_PAT (1U<<14)
#define VMX_ENTRY_CTLS_LOAD_EFER (1U<<15)
/* VMX entry/exit Interrupt info */
#define VMX_INT_INFO_ERR_CODE_VALID (1<<11)
#define VMX_INT_INFO_VALID (1<<31)
#define VMX_INT_TYPE_MASK (0x700)
#define VMX_INT_TYPE_EXT_INT 0
#define VMX_INT_TYPE_NMI 2
#define VMX_INT_TYPE_HW_EXP 3
#define VMX_INT_TYPE_SW_EXP 6
#define VMX_INT_INFO_ERR_CODE_VALID (1U<<11)
#define VMX_INT_INFO_VALID (1U<<31)
#define VMX_INT_TYPE_MASK (0x700U)
#define VMX_INT_TYPE_EXT_INT 0U
#define VMX_INT_TYPE_NMI 2U
#define VMX_INT_TYPE_HW_EXP 3U
#define VMX_INT_TYPE_SW_EXP 6U
/*VM exit qulifications for APIC-access
* Access type:
@ -376,19 +376,19 @@
* 15 = guest-physical access for an instructon fetch or during
* instruction execution
*/
#define APIC_ACCESS_TYPE(qual) (((qual) >> 12) & 0xF)
#define APIC_ACCESS_OFFSET(qual) ((qual) & 0xFFF)
#define APIC_ACCESS_TYPE(qual) (((qual) >> 12) & 0xFU)
#define APIC_ACCESS_OFFSET(qual) ((qual) & 0xFFFU)
#define VM_SUCCESS 0
#define VM_FAIL -1
#define VMX_VMENTRY_FAIL 0x80000000
#define VMX_VMENTRY_FAIL 0x80000000U
#ifndef ASSEMBLER
#define RFLAGS_C (1<<0)
#define RFLAGS_Z (1<<6)
#define RFLAGS_C (1U<<0)
#define RFLAGS_Z (1U<<6)
/* CR0 bits hv want to trap to track status change */
#define CR0_TRAP_MASK (CR0_PE | CR0_PG | CR0_WP)
@ -398,7 +398,7 @@
/* CR4 bits hv want to trap to track status change */
#define CR4_TRAP_MASK (CR4_PSE | CR4_PAE)
#define VMX_SUPPORT_UNRESTRICTED_GUEST (1<<5)
#define VMX_SUPPORT_UNRESTRICTED_GUEST (1U<<5)
/* External Interfaces */
int exec_vmxon_instr(uint32_t pcpu_id);

226
hypervisor/include/arch/x86/vtd.h
View File

@ -10,89 +10,89 @@
* Intel IOMMU register specification per version 1.0 public spec.
*/
#define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
#define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
#define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
#define DMAR_GCMD_REG 0x18 /* Global command register */
#define DMAR_GSTS_REG 0x1c /* Global status register */
#define DMAR_RTADDR_REG 0x20 /* Root entry table */
#define DMAR_CCMD_REG 0x28 /* Context command reg */
#define DMAR_FSTS_REG 0x34 /* Fault Status register */
#define DMAR_FECTL_REG 0x38 /* Fault control register */
#define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
#define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
#define DMAR_FEUADDR_REG 0x44 /* Upper address register */
#define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
#define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
#define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
#define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
#define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
#define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
#define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
#define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
#define DMAR_VER_REG 0x0U /* Arch version supported by this IOMMU */
#define DMAR_CAP_REG 0x8U /* Hardware supported capabilities */
#define DMAR_ECAP_REG 0x10U /* Extended capabilities supported */
#define DMAR_GCMD_REG 0x18U /* Global command register */
#define DMAR_GSTS_REG 0x1cU /* Global status register */
#define DMAR_RTADDR_REG 0x20U /* Root entry table */
#define DMAR_CCMD_REG 0x28U /* Context command reg */
#define DMAR_FSTS_REG 0x34U /* Fault Status register */
#define DMAR_FECTL_REG 0x38U /* Fault control register */
#define DMAR_FEDATA_REG 0x3cU /* Fault event interrupt data register */
#define DMAR_FEADDR_REG 0x40U /* Fault event interrupt addr register */
#define DMAR_FEUADDR_REG 0x44U /* Upper address register */
#define DMAR_AFLOG_REG 0x58U /* Advanced Fault control */
#define DMAR_PMEN_REG 0x64U /* Enable Protected Memory Region */
#define DMAR_PLMBASE_REG 0x68U /* PMRR Low addr */
#define DMAR_PLMLIMIT_REG 0x6cU /* PMRR low limit */
#define DMAR_PHMBASE_REG 0x70U /* pmrr high base addr */
#define DMAR_PHMLIMIT_REG 0x78U /* pmrr high limit */
#define DMAR_IQH_REG 0x80U /* Invalidation queue head register */
#define DMAR_IQT_REG 0x88U /* Invalidation queue tail register */
#define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */
#define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
#define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
#define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
#define DMAR_IQA_REG 0x90U /* Invalidation queue addr register */
#define DMAR_ICS_REG 0x9cU /* Invalidation complete status register */
#define DMAR_IRTA_REG 0xb8U /* Interrupt remapping table addr register */
#define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
#define DMAR_VER_MINOR(v) ((v) & 0x0f)
#define DMAR_VER_MAJOR(v) (((v) & 0xf0U) >> 4)
#define DMAR_VER_MINOR(v) ((v) & 0x0fU)
/*
* Decoding Capability Register
*/
#define iommu_cap_pi(c) (((c) >> 59) & 1)
#define iommu_cap_read_drain(c) (((c) >> 55) & 1)
#define iommu_cap_write_drain(c) (((c) >> 54) & 1)
#define iommu_cap_max_amask_val(c) (((c) >> 48) & 0x3f)
#define iommu_cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
#define iommu_cap_pgsel_inv(c) (((c) >> 39) & 1)
#define iommu_cap_pi(c) (((c) >> 59) & 1UL)
#define iommu_cap_read_drain(c) (((c) >> 55) & 1UL)
#define iommu_cap_write_drain(c) (((c) >> 54) & 1UL)
#define iommu_cap_max_amask_val(c) (((c) >> 48) & 0x3fUL)
#define iommu_cap_num_fault_regs(c) ((((c) >> 40) & 0xffUL) + 1)
#define iommu_cap_pgsel_inv(c) (((c) >> 39) & 1UL)
#define iommu_cap_super_page_val(c) (((c) >> 34) & 0xf)
#define iommu_cap_super_page_val(c) (((c) >> 34) & 0xfUL)
#define iommu_cap_super_offset(c) \
(((find_first_bit(&iommu_cap_super_page_val(c), 4)) \
* OFFSET_STRIDE) + 21)
#define iommu_cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
#define iommu_cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ffUL) * 16)
#define iommu_cap_max_fault_reg_offset(c) \
(iommu_cap_fault_reg_offset(c) + iommu_cap_num_fault_regs(c) * 16)
#define iommu_cap_zlr(c) (((c) >> 22) & 1)
#define iommu_cap_isoch(c) (((c) >> 23) & 1)
#define iommu_cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
#define iommu_cap_sagaw(c) (((c) >> 8) & 0x1f)
#define iommu_cap_caching_mode(c) (((c) >> 7) & 1)
#define iommu_cap_phmr(c) (((c) >> 6) & 1)
#define iommu_cap_plmr(c) (((c) >> 5) & 1)
#define iommu_cap_rwbf(c) (((c) >> 4) & 1)
#define iommu_cap_afl(c) (((c) >> 3) & 1)
#define iommu_cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
#define iommu_cap_zlr(c) (((c) >> 22) & 1UL)
#define iommu_cap_isoch(c) (((c) >> 23) & 1UL)
#define iommu_cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1UL)
#define iommu_cap_sagaw(c) (((c) >> 8) & 0x1fUL)
#define iommu_cap_caching_mode(c) (((c) >> 7) & 1UL)
#define iommu_cap_phmr(c) (((c) >> 6) & 1UL)
#define iommu_cap_plmr(c) (((c) >> 5) & 1UL)
#define iommu_cap_rwbf(c) (((c) >> 4) & 1UL)
#define iommu_cap_afl(c) (((c) >> 3) & 1UL)
#define iommu_cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7UL)))
/*
* Decoding Extended Capability Register
*/
#define iommu_ecap_c(c) (((c) >> 0) & 1)
#define iommu_ecap_qi(c) (((c) >> 1) & 1)
#define iommu_ecap_dt(c) (((c) >> 2) & 1)
#define iommu_ecap_ir(c) (((c) >> 3) & 1)
#define iommu_ecap_eim(c) (((c) >> 4) & 1)
#define iommu_ecap_pt(c) (((c) >> 6) & 1)
#define iommu_ecap_sc(c) (((c) >> 7) & 1)
#define iommu_ecap_iro(c) (((c) >> 8) & 0x3ff)
#define iommu_ecap_mhmv(c) (((c) >> 20) & 0xf)
#define iommu_ecap_ecs(c) (((c) >> 24) & 1)
#define iommu_ecap_mts(c) (((c) >> 25) & 1)
#define iommu_ecap_nest(c) (((c) >> 26) & 1)
#define iommu_ecap_dis(c) (((c) >> 27) & 1)
#define iommu_ecap_prs(c) (((c) >> 29) & 1)
#define iommu_ecap_ers(c) (((c) >> 30) & 1)
#define iommu_ecap_srs(c) (((c) >> 31) & 1)
#define iommu_ecap_nwfs(c) (((c) >> 33) & 1)
#define iommu_ecap_eafs(c) (((c) >> 34) & 1)
#define iommu_ecap_pss(c) (((c) >> 35) & 0x1f)
#define iommu_ecap_pasid(c) (((c) >> 40) & 1)
#define iommu_ecap_dit(c) (((c) >> 41) & 1)
#define iommu_ecap_pds(c) (((c) >> 42) & 1)
#define iommu_ecap_c(c) (((c) >> 0) & 1UL)
#define iommu_ecap_qi(c) (((c) >> 1) & 1UL)
#define iommu_ecap_dt(c) (((c) >> 2) & 1UL)
#define iommu_ecap_ir(c) (((c) >> 3) & 1UL)
#define iommu_ecap_eim(c) (((c) >> 4) & 1UL)
#define iommu_ecap_pt(c) (((c) >> 6) & 1UL)
#define iommu_ecap_sc(c) (((c) >> 7) & 1UL)
#define iommu_ecap_iro(c) (((c) >> 8) & 0x3ffUL)
#define iommu_ecap_mhmv(c) (((c) >> 20) & 0xfUL)
#define iommu_ecap_ecs(c) (((c) >> 24) & 1UL)
#define iommu_ecap_mts(c) (((c) >> 25) & 1UL)
#define iommu_ecap_nest(c) (((c) >> 26) & 1UL)
#define iommu_ecap_dis(c) (((c) >> 27) & 1UL)
#define iommu_ecap_prs(c) (((c) >> 29) & 1UL)
#define iommu_ecap_ers(c) (((c) >> 30) & 1UL)
#define iommu_ecap_srs(c) (((c) >> 31) & 1UL)
#define iommu_ecap_nwfs(c) (((c) >> 33) & 1UL)
#define iommu_ecap_eafs(c) (((c) >> 34) & 1UL)
#define iommu_ecap_pss(c) (((c) >> 35) & 0x1fUL)
#define iommu_ecap_pasid(c) (((c) >> 40) & 1UL)
#define iommu_ecap_dit(c) (((c) >> 41) & 1UL)
#define iommu_ecap_pds(c) (((c) >> 42) & 1UL)
/* PMEN_REG */
#define DMA_PMEN_EPM (((uint32_t)1)<<31)
@ -121,68 +121,68 @@
#define DMA_GSTS_CFIS (((uint32_t)1) << 23)
/* CCMD_REG */
#define DMA_CCMD_ICC (((uint64_t)1) << 63)
#define DMA_CCMD_ICC_32 (((uint32_t)1) << 31)
#define DMA_CCMD_GLOBAL_INVL (((uint64_t)1) << 61)
#define DMA_CCMD_DOMAIN_INVL (((uint64_t)2) << 61)
#define DMA_CCMD_DEVICE_INVL (((uint64_t)3) << 61)
#define DMA_CCMD_FM(m) (((uint64_t)((m) & 0x3)) << 32)
#define DMA_CCMD_MASK_NOBIT 0
#define DMA_CCMD_MASK_1BIT 1
#define DMA_CCMD_MASK_2BIT 2
#define DMA_CCMD_MASK_3BIT 3
#define DMA_CCMD_SID(s) (((uint64_t)((s) & 0xffff)) << 16)
#define DMA_CCMD_DID(d) ((uint64_t)((d) & 0xffff))
#define DMA_CCMD_GET_CAIG_32(v) (((uint32_t)(v) >> 27) & 0x3)
#define DMA_CCMD_ICC (((uint64_t)1UL) << 63)
#define DMA_CCMD_ICC_32 (((uint32_t)1UL) << 31)
#define DMA_CCMD_GLOBAL_INVL (((uint64_t)1UL) << 61)
#define DMA_CCMD_DOMAIN_INVL (((uint64_t)2UL) << 61)
#define DMA_CCMD_DEVICE_INVL (((uint64_t)3UL) << 61)
#define DMA_CCMD_FM(m) (((uint64_t)((m) & 0x3UL)) << 32)
#define DMA_CCMD_MASK_NOBIT 0UL
#define DMA_CCMD_MASK_1BIT 1UL
#define DMA_CCMD_MASK_2BIT 2UL
#define DMA_CCMD_MASK_3BIT 3UL
#define DMA_CCMD_SID(s) (((uint64_t)((s) & 0xffffUL)) << 16)
#define DMA_CCMD_DID(d) ((uint64_t)((d) & 0xffffUL))
#define DMA_CCMD_GET_CAIG_32(v) (((uint32_t)(v) >> 27) & 0x3U)
/* IOTLB_REG */
#define DMA_IOTLB_IVT (((uint64_t)1) << 63)
#define DMA_IOTLB_IVT_32 (((uint32_t)1) << 31)
#define DMA_IOTLB_GLOBAL_INVL (((uint64_t)1) << 60)
#define DMA_IOTLB_DOMAIN_INVL (((uint64_t)2) << 60)
#define DMA_IOTLB_PAGE_INVL (((uint64_t)3) << 60)
#define DMA_IOTLB_DR (((uint64_t)1) << 49)
#define DMA_IOTLB_DW (((uint64_t)1) << 48)
#define DMA_IOTLB_IVT (((uint64_t)1UL) << 63)
#define DMA_IOTLB_IVT_32 (((uint32_t)1U) << 31)
#define DMA_IOTLB_GLOBAL_INVL (((uint64_t)1UL) << 60)
#define DMA_IOTLB_DOMAIN_INVL (((uint64_t)2UL) << 60)
#define DMA_IOTLB_PAGE_INVL (((uint64_t)3UL) << 60)
#define DMA_IOTLB_DR (((uint64_t)1UL) << 49)
#define DMA_IOTLB_DW (((uint64_t)1UL) << 48)
#define DMA_IOTLB_DID(d) \
(((uint64_t)((d) & 0xffff)) << 32)
#define DMA_IOTLB_GET_IAIG_32(v) (((uint32_t)(v) >> 25) & 0x3)
(((uint64_t)((d) & 0xffffUL)) << 32)
#define DMA_IOTLB_GET_IAIG_32(v) (((uint32_t)(v) >> 25) & 0x3U)
/* INVALIDATE_ADDRESS_REG */
#define DMA_IOTLB_INVL_ADDR_AM(m) ((uint64_t)((m) & 0x3f))
#define DMA_IOTLB_INVL_ADDR_IH_UNMODIFIED (((uint64_t)1) << 6)
#define DMA_IOTLB_INVL_ADDR_AM(m) ((uint64_t)((m) & 0x3fUL))
#define DMA_IOTLB_INVL_ADDR_IH_UNMODIFIED (((uint64_t)1UL) << 6)
/* FECTL_REG */
#define DMA_FECTL_IM (((uint32_t)1) << 31)
#define DMA_FECTL_IM (((uint32_t)1U) << 31)
/* FSTS_REG */
#define DMA_FSTS_PFO(s) (((s) >> 0) & 1)
#define DMA_FSTS_PPF(s) (((s) >> 1) & 1)
#define DMA_FSTS_AFO(s) (((s) >> 2) & 1)
#define DMA_FSTS_APF(s) (((s) >> 3) & 1)
#define DMA_FSTS_IQE(s) (((s) >> 4) & 1)
#define DMA_FSTS_ICE(s) (((s) >> 5) & 1)
#define DMA_FSTS_ITE(s) (((s) >> 6) & 1)
#define DMA_FSTS_PRO(s) (((s) >> 7) & 1)
#define DMA_FSTS_FRI(s) (((s) >> 8) & 0xFF)
#define DMA_FSTS_PFO(s) (((s) >> 0) & 1U)
#define DMA_FSTS_PPF(s) (((s) >> 1) & 1U)
#define DMA_FSTS_AFO(s) (((s) >> 2) & 1U)
#define DMA_FSTS_APF(s) (((s) >> 3) & 1U)
#define DMA_FSTS_IQE(s) (((s) >> 4) & 1U)
#define DMA_FSTS_ICE(s) (((s) >> 5) & 1U)
#define DMA_FSTS_ITE(s) (((s) >> 6) & 1U)
#define DMA_FSTS_PRO(s) (((s) >> 7) & 1U)
#define DMA_FSTS_FRI(s) (((s) >> 8) & 0xFFU)
/* FRCD_REGs: upper 64 bits*/
#define DMA_FRCD_UP_F(r) (((r) >> 63) & 1)
#define DMA_FRCD_UP_T(r) (((r) >> 62) & 1)
#define DMA_FRCD_UP_AT(r) (((r) >> 60) & 3)
#define DMA_FRCD_UP_PASID(r) (((r) >> 40) & 0xfffff)
#define DMA_FRCD_UP_FR(r) (((r) >> 32) & 0xff)
#define DMA_FRCD_UP_PP(r) (((r) >> 31) & 1)
#define DMA_FRCD_UP_EXE(r) (((r) >> 30) & 1)
#define DMA_FRCD_UP_PRIV(r) (((r) >> 29) & 1)
#define DMA_FRCD_UP_SID(r) (((r) >> 0) & 0xffff)
#define DMA_FRCD_UP_F(r) (((r) >> 63) & 1UL)
#define DMA_FRCD_UP_T(r) (((r) >> 62) & 1UL)
#define DMA_FRCD_UP_AT(r) (((r) >> 60) & 3UL)
#define DMA_FRCD_UP_PASID(r) (((r) >> 40) & 0xfffffUL)
#define DMA_FRCD_UP_FR(r) (((r) >> 32) & 0xffUL)
#define DMA_FRCD_UP_PP(r) (((r) >> 31) & 1UL)
#define DMA_FRCD_UP_EXE(r) (((r) >> 30) & 1UL)
#define DMA_FRCD_UP_PRIV(r) (((r) >> 29) & 1UL)
#define DMA_FRCD_UP_SID(r) (((r) >> 0) & 0xffffUL)
#define DMAR_CONTEXT_TRANSLATION_TYPE_TRANSLATED 0x00
#define DMAR_CONTEXT_TRANSLATION_TYPE_RESERVED 0x01
#define DMAR_CONTEXT_TRANSLATION_TYPE_PASSED_THROUGH 0x02
#define DMAR_CONTEXT_TRANSLATION_TYPE_TRANSLATED 0x00U
#define DMAR_CONTEXT_TRANSLATION_TYPE_RESERVED 0x01U
#define DMAR_CONTEXT_TRANSLATION_TYPE_PASSED_THROUGH 0x02U
#define DRHD_FLAG_INCLUDE_PCI_ALL_MASK (1)
#define DRHD_FLAG_INCLUDE_PCI_ALL_MASK (1U)
#define DEVFUN(dev, fun) (((dev & 0x1F) << 3) | ((fun & 0x7)))
#define DEVFUN(dev, fun) (((dev & 0x1FU) << 3) | ((fun & 0x7U)))
struct dmar_dev_scope {
uint8_t bus;