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HV: vmx: convert hexadecimals used in bitops to unsigned

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Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Junjie Mao
2018-06-19 18:32:16 +08:00
committed by lijinxia
parent 41a1035f9b
commit d705970eb2
5 changed files with 457 additions and 457 deletions
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4
hypervisor/arch/x86/ept.c
View File

@@ -308,7 +308,7 @@ static int dm_emulate_mmio_pre(struct vcpu *vcpu, uint64_t exit_qual)
return status;
vcpu->req.reqs.mmio_request.value = vcpu->mmio.value;
/* XXX: write access while EPT perm RX -> WP */
if ((exit_qual & 0x38) == 0x28)
if ((exit_qual & 0x38UL) == 0x28UL)
vcpu->req.type = REQ_WP;
}
@@ -334,7 +334,7 @@ int ept_violation_vmexit_handler(struct vcpu *vcpu)
exit_qual = vcpu->arch_vcpu.exit_qualification;
/* Specify if read or write operation */
if ((exit_qual & 0x2) != 0U) {
if ((exit_qual & 0x2UL) != 0UL) {
/* Write operation */
mmio->read_write = HV_MEM_IO_WRITE;

30
hypervisor/arch/x86/vmx.c
View File

@@ -255,7 +255,7 @@ uint32_t get_cs_access_rights(void)
asm volatile ("movw %%cs, %%ax" : "=a" (sel_value));
asm volatile ("lar %%eax, %%eax" : "=a" (usable_ar) : "a"(sel_value));
usable_ar = usable_ar >> 8;
usable_ar &= 0xf0ff; /* clear bits 11:8 */
usable_ar &= 0xf0ffU; /* clear bits 11:8 */
return usable_ar;
}
@@ -620,8 +620,8 @@ static void init_guest_state(struct vcpu *vcpu)
value32 = gdtb.limit;
if (((gdtb.base >> 47) & 0x1) != 0U)
gdtb.base |= 0xffff000000000000ull;
if (((gdtb.base >> 47) & 0x1UL) != 0UL)
gdtb.base |= 0xffff000000000000UL;
base = gdtb.base;
@@ -655,8 +655,8 @@ static void init_guest_state(struct vcpu *vcpu)
/* Limit */
limit = idtb.limit;
if (((idtb.base >> 47) & 0x1) != 0U)
idtb.base |= 0xffff000000000000ull;
if (((idtb.base >> 47) & 0x1UL) != 0UL)
idtb.base |= 0xffff000000000000UL;
/* Base */
base = idtb.base;
@@ -953,8 +953,8 @@ static void init_host_state(__unused struct vcpu *vcpu)
asm volatile ("sgdt %0"::"m" (gdtb));
value32 = gdtb.limit;
if (((gdtb.base >> 47) & 0x1) != 0U)
gdtb.base |= 0xffff000000000000ull;
if (((gdtb.base >> 47) & 0x1UL) != 0UL)
gdtb.base |= 0xffff000000000000UL;
/* Set up the guest and host GDTB base fields with current GDTB base */
field = VMX_HOST_GDTR_BASE;
@@ -963,17 +963,17 @@ static void init_host_state(__unused struct vcpu *vcpu)
/* TODO: Should guest TR point to host TR ? */
trbase = gdtb.base + tr_sel;
if (((trbase >> 47) & 0x1) != 0U)
trbase |= 0xffff000000000000ull;
if (((trbase >> 47) & 0x1UL) != 0UL)
trbase |= 0xffff000000000000UL;
/* SS segment override */
asm volatile ("mov %0,%%rax\n"
".byte 0x36\n"
"movq (%%rax),%%rax\n":"=a" (trbase_lo):"0"(trbase)
);
realtrbase = ((trbase_lo >> 16) & (0x0ffff)) |
(((trbase_lo >> 32) & 0x000000ff) << 16) |
(((trbase_lo >> 56) & 0xff) << 24);
realtrbase = ((trbase_lo >> 16) & (0x0ffffUL)) |
(((trbase_lo >> 32) & 0x000000ffUL) << 16) |
(((trbase_lo >> 56) & 0xffUL) << 24);
/* SS segment override for upper32 bits of base in ia32e mode */
asm volatile ("mov %0,%%rax\n"
@@ -989,8 +989,8 @@ static void init_host_state(__unused struct vcpu *vcpu)
/* Obtain the current interrupt descriptor table base */
asm volatile ("sidt %0"::"m" (idtb));
/* base */
if (((idtb.base >> 47) & 0x1) != 0U)
idtb.base |= 0xffff000000000000ull;
if (((idtb.base >> 47) & 0x1UL) != 0UL)
idtb.base |= 0xffff000000000000UL;
field = VMX_HOST_IDTR_BASE;
exec_vmwrite(field, idtb.base);
@@ -1210,7 +1210,7 @@ static void init_exec_ctrl(struct vcpu *vcpu)
* TODO: introduce API to make this data driven based
* on VMX_EPT_VPID_CAP
*/
value64 = vm->arch_vm.nworld_eptp | (3 << 3) | 6;
value64 = vm->arch_vm.nworld_eptp | (3UL << 3) | 6UL;
exec_vmwrite64(VMX_EPT_POINTER_FULL, value64);
pr_dbg("VMX_EPT_POINTER: 0x%016llx ", value64);

16
hypervisor/arch/x86/vtd.c
View File

@@ -407,10 +407,10 @@ static void dmar_register_hrhd(struct dmar_drhd_rt *dmar_uint)
#endif
/* check capability */
if ((iommu_cap_super_page_val(dmar_uint->cap) & 0x1) == 0)
if ((iommu_cap_super_page_val(dmar_uint->cap) & 0x1UL) == 0)
dev_dbg(ACRN_DBG_IOMMU, "dmar uint doesn't support 2MB page!");
if ((iommu_cap_super_page_val(dmar_uint->cap) & 0x2) == 0)
if ((iommu_cap_super_page_val(dmar_uint->cap) & 0x2UL) == 0)
dev_dbg(ACRN_DBG_IOMMU, "dmar uint doesn't support 1GB page!");
/* when the hardware support snoop control,
@@ -675,7 +675,7 @@ static void dmar_fault_msi_write(struct dmar_drhd_rt *dmar_uint,
/* redirection hint: 0
* destination mode: 0
*/
addr_low = 0xFEE00000 | ((lapic_id & 0xFF) << 12);
addr_low = 0xFEE00000U | ((lapic_id & 0xFFU) << 12);
IOMMU_LOCK(dmar_uint);
iommu_write32(dmar_uint, DMAR_FEDATA_REG, data);
@@ -722,8 +722,8 @@ static void fault_record_analysis(__unused uint64_t low, uint64_t high)
(DMA_FRCD_UP_T(high) != 0U) ? "Read/Atomic" : "Write",
DMA_FRCD_UP_FR(high),
DMA_FRCD_UP_SID(high) >> 8,
(DMA_FRCD_UP_SID(high) >> 3) & 0x1f,
DMA_FRCD_UP_SID(high) & 0x7,
(DMA_FRCD_UP_SID(high) >> 3) & 0x1fUL,
DMA_FRCD_UP_SID(high) & 0x7UL,
low);
#if DBG_IOMMU
if (iommu_ecap_dt(dmar_uint->ecap))
@@ -919,13 +919,13 @@ static int add_iommu_device(struct iommu_domain *domain, uint16_t segment,
dmar_uint = device_to_dmaru(segment, bus, devfun);
if (dmar_uint == NULL) {
pr_err("no dmar unit found for device:0x%x:%x.%x",
bus, devfun >> 3, devfun & 0x7);
bus, devfun >> 3, devfun & 0x7U);
return 1;
}
if (dmar_uint->drhd->ignore) {
dev_dbg(ACRN_DBG_IOMMU, "device is ignored :0x%x:%x.%x",
bus, devfun >> 3, devfun & 0x7);
bus, devfun >> 3, devfun & 0x7U);
return 0;
}
@@ -987,7 +987,7 @@ static int add_iommu_device(struct iommu_domain *domain, uint16_t segment,
pr_err("%s: context entry@0x%llx (Lower:%x) ",
__func__, context_entry, context_entry->lower);
pr_err("already present for %x:%x.%x",
bus, devfun >> 3, devfun & 0x7);
bus, devfun >> 3, devfun & 0x7U);
return 1;
}