mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-09-23 17:58:30 +00:00
HV: vmx: convert hexadecimals used in bitops to unsigned
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
@@ -308,7 +308,7 @@ static int dm_emulate_mmio_pre(struct vcpu *vcpu, uint64_t exit_qual)
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return status;
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vcpu->req.reqs.mmio_request.value = vcpu->mmio.value;
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/* XXX: write access while EPT perm RX -> WP */
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if ((exit_qual & 0x38) == 0x28)
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if ((exit_qual & 0x38UL) == 0x28UL)
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vcpu->req.type = REQ_WP;
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}
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@@ -334,7 +334,7 @@ int ept_violation_vmexit_handler(struct vcpu *vcpu)
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exit_qual = vcpu->arch_vcpu.exit_qualification;
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/* Specify if read or write operation */
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if ((exit_qual & 0x2) != 0U) {
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if ((exit_qual & 0x2UL) != 0UL) {
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/* Write operation */
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mmio->read_write = HV_MEM_IO_WRITE;
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@@ -255,7 +255,7 @@ uint32_t get_cs_access_rights(void)
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asm volatile ("movw %%cs, %%ax" : "=a" (sel_value));
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asm volatile ("lar %%eax, %%eax" : "=a" (usable_ar) : "a"(sel_value));
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usable_ar = usable_ar >> 8;
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usable_ar &= 0xf0ff; /* clear bits 11:8 */
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usable_ar &= 0xf0ffU; /* clear bits 11:8 */
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return usable_ar;
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}
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@@ -620,8 +620,8 @@ static void init_guest_state(struct vcpu *vcpu)
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value32 = gdtb.limit;
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if (((gdtb.base >> 47) & 0x1) != 0U)
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gdtb.base |= 0xffff000000000000ull;
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if (((gdtb.base >> 47) & 0x1UL) != 0UL)
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gdtb.base |= 0xffff000000000000UL;
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base = gdtb.base;
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@@ -655,8 +655,8 @@ static void init_guest_state(struct vcpu *vcpu)
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/* Limit */
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limit = idtb.limit;
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if (((idtb.base >> 47) & 0x1) != 0U)
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idtb.base |= 0xffff000000000000ull;
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if (((idtb.base >> 47) & 0x1UL) != 0UL)
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idtb.base |= 0xffff000000000000UL;
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/* Base */
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base = idtb.base;
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@@ -953,8 +953,8 @@ static void init_host_state(__unused struct vcpu *vcpu)
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asm volatile ("sgdt %0"::"m" (gdtb));
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value32 = gdtb.limit;
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if (((gdtb.base >> 47) & 0x1) != 0U)
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gdtb.base |= 0xffff000000000000ull;
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if (((gdtb.base >> 47) & 0x1UL) != 0UL)
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gdtb.base |= 0xffff000000000000UL;
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/* Set up the guest and host GDTB base fields with current GDTB base */
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field = VMX_HOST_GDTR_BASE;
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@@ -963,17 +963,17 @@ static void init_host_state(__unused struct vcpu *vcpu)
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/* TODO: Should guest TR point to host TR ? */
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trbase = gdtb.base + tr_sel;
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if (((trbase >> 47) & 0x1) != 0U)
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trbase |= 0xffff000000000000ull;
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if (((trbase >> 47) & 0x1UL) != 0UL)
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trbase |= 0xffff000000000000UL;
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/* SS segment override */
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asm volatile ("mov %0,%%rax\n"
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".byte 0x36\n"
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"movq (%%rax),%%rax\n":"=a" (trbase_lo):"0"(trbase)
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);
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realtrbase = ((trbase_lo >> 16) & (0x0ffff)) |
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(((trbase_lo >> 32) & 0x000000ff) << 16) |
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(((trbase_lo >> 56) & 0xff) << 24);
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realtrbase = ((trbase_lo >> 16) & (0x0ffffUL)) |
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(((trbase_lo >> 32) & 0x000000ffUL) << 16) |
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(((trbase_lo >> 56) & 0xffUL) << 24);
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/* SS segment override for upper32 bits of base in ia32e mode */
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asm volatile ("mov %0,%%rax\n"
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@@ -989,8 +989,8 @@ static void init_host_state(__unused struct vcpu *vcpu)
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/* Obtain the current interrupt descriptor table base */
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asm volatile ("sidt %0"::"m" (idtb));
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/* base */
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if (((idtb.base >> 47) & 0x1) != 0U)
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idtb.base |= 0xffff000000000000ull;
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if (((idtb.base >> 47) & 0x1UL) != 0UL)
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idtb.base |= 0xffff000000000000UL;
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field = VMX_HOST_IDTR_BASE;
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exec_vmwrite(field, idtb.base);
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@@ -1210,7 +1210,7 @@ static void init_exec_ctrl(struct vcpu *vcpu)
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* TODO: introduce API to make this data driven based
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* on VMX_EPT_VPID_CAP
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*/
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value64 = vm->arch_vm.nworld_eptp | (3 << 3) | 6;
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value64 = vm->arch_vm.nworld_eptp | (3UL << 3) | 6UL;
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exec_vmwrite64(VMX_EPT_POINTER_FULL, value64);
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pr_dbg("VMX_EPT_POINTER: 0x%016llx ", value64);
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@@ -407,10 +407,10 @@ static void dmar_register_hrhd(struct dmar_drhd_rt *dmar_uint)
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#endif
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/* check capability */
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if ((iommu_cap_super_page_val(dmar_uint->cap) & 0x1) == 0)
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if ((iommu_cap_super_page_val(dmar_uint->cap) & 0x1UL) == 0)
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dev_dbg(ACRN_DBG_IOMMU, "dmar uint doesn't support 2MB page!");
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if ((iommu_cap_super_page_val(dmar_uint->cap) & 0x2) == 0)
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if ((iommu_cap_super_page_val(dmar_uint->cap) & 0x2UL) == 0)
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dev_dbg(ACRN_DBG_IOMMU, "dmar uint doesn't support 1GB page!");
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/* when the hardware support snoop control,
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@@ -675,7 +675,7 @@ static void dmar_fault_msi_write(struct dmar_drhd_rt *dmar_uint,
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/* redirection hint: 0
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* destination mode: 0
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*/
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addr_low = 0xFEE00000 | ((lapic_id & 0xFF) << 12);
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addr_low = 0xFEE00000U | ((lapic_id & 0xFFU) << 12);
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IOMMU_LOCK(dmar_uint);
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iommu_write32(dmar_uint, DMAR_FEDATA_REG, data);
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@@ -722,8 +722,8 @@ static void fault_record_analysis(__unused uint64_t low, uint64_t high)
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(DMA_FRCD_UP_T(high) != 0U) ? "Read/Atomic" : "Write",
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DMA_FRCD_UP_FR(high),
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DMA_FRCD_UP_SID(high) >> 8,
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(DMA_FRCD_UP_SID(high) >> 3) & 0x1f,
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DMA_FRCD_UP_SID(high) & 0x7,
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(DMA_FRCD_UP_SID(high) >> 3) & 0x1fUL,
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DMA_FRCD_UP_SID(high) & 0x7UL,
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low);
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#if DBG_IOMMU
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if (iommu_ecap_dt(dmar_uint->ecap))
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@@ -919,13 +919,13 @@ static int add_iommu_device(struct iommu_domain *domain, uint16_t segment,
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dmar_uint = device_to_dmaru(segment, bus, devfun);
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if (dmar_uint == NULL) {
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pr_err("no dmar unit found for device:0x%x:%x.%x",
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bus, devfun >> 3, devfun & 0x7);
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bus, devfun >> 3, devfun & 0x7U);
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return 1;
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}
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if (dmar_uint->drhd->ignore) {
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dev_dbg(ACRN_DBG_IOMMU, "device is ignored :0x%x:%x.%x",
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bus, devfun >> 3, devfun & 0x7);
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bus, devfun >> 3, devfun & 0x7U);
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return 0;
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}
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@@ -987,7 +987,7 @@ static int add_iommu_device(struct iommu_domain *domain, uint16_t segment,
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pr_err("%s: context entry@0x%llx (Lower:%x) ",
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__func__, context_entry, context_entry->lower);
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pr_err("already present for %x:%x.%x",
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bus, devfun >> 3, devfun & 0x7);
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bus, devfun >> 3, devfun & 0x7U);
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return 1;
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}
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