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dm: relocate memory slot for SW SRAM region

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GPA base of SW SRAM can't be hardcoded as physical address
  of SW SRAM(HPA), as this HPA may vary on different platform.

  This patch reserves a dedicated memory slot[GPA: 2G - 8M, 2G)
  as SW SRAM region.

Tracked-On: #5649
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
This commit is contained in:
Yonghua Huang
2021-01-26 16:16:19 +08:00
committed by wenlingz
parent 154a446c5c
commit d8b754e53a
3 changed files with 31 additions and 22 deletions
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3
devicemodel/include/pci_core.h
View File

@@ -48,6 +48,9 @@
#define PCI_EMUL_MEMBASE64 0x100000000UL /* 4GB */
#define PCI_EMUL_MEMLIMIT64 0x140000000UL /* 5GB */
#define SOFTWARE_SRAM_MAX_SIZE 0x00800000UL
#define SOFTWARE_SRAM_BASE_GPA (PCI_EMUL_MEMBASE32 - SOFTWARE_SRAM_MAX_SIZE)
/* Currently,only gvt need reserved bar regions,
* so just hardcode REGION_NUMS=5 here
*/

5
devicemodel/include/rtct.h
View File

@@ -17,11 +17,6 @@
#define RTCT_ENTRY_TYPE_RT_IOMMU 8U
#define RTCT_ENTRY_TYPE_MEM_HIERARCHY_LATENCY 9U
/* TODO: Move to high-memory region. */
#define SOFTWARE_SRAM_BASE_HPA 0x40080000UL
#define SOFTWARE_SRAM_BASE_GPA 0x40080000UL
#define SOFTWARE_SRAM_MAX_SIZE 0x00800000UL
struct rtct_entry {
uint16_t size;
uint16_t format;