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hv: mmu: move arch specific parts into cpu.h

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Move Cache/TLB arch specific parts into cpu.h
After this change, we should not expose arch specific parts out from mmu.h

Tracked-On: #5830
Signed-off-by: Li Fei1 <fei1.li@intel.com>
This commit is contained in:
Li Fei1 2021-04-23 14:50:14 +08:00 committed by wenlingz
parent d6362b6e0a
commit d94582389e
4 changed files with 22 additions and 25 deletions
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3
hypervisor/arch/x86/vtd.c
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@ -10,8 +10,7 @@
#include <errno.h> #include <errno.h>
#include <asm/lib/bits.h> #include <asm/lib/bits.h>
#include <asm/lib/spinlock.h> #include <asm/lib/spinlock.h>
#include <asm/page.h> #include <asm/cpu_caps.h>
#include <asm/pgtable.h>
#include <irq.h> #include <irq.h>
#include <asm/irq.h> #include <asm/irq.h>
#include <asm/io.h> #include <asm/io.h>

2
hypervisor/debug/uart16550.c
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@ -7,9 +7,9 @@
#include <types.h> #include <types.h>
#include <asm/lib/spinlock.h> #include <asm/lib/spinlock.h>
#include <pci.h> #include <pci.h>
#include <asm/pgtable.h>
#include <uart16550.h> #include <uart16550.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/cpu.h>
#include <asm/mmu.h> #include <asm/mmu.h>
#define MAX_BDF_LEN 8 #define MAX_BDF_LEN 8

20
hypervisor/include/arch/x86/asm/cpu.h
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@ -546,6 +546,26 @@ static inline void cpu_memory_barrier(void)
asm volatile ("mfence\n" : : : "memory"); asm volatile ("mfence\n" : : : "memory");
} }
static inline void invlpg(unsigned long addr)
{
asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
}
static inline void cache_flush_invalidate_all(void)
{
asm volatile (" wbinvd\n" : : : "memory");
}
static inline void clflush(const volatile void *p)
{
asm volatile ("clflush (%0)" :: "r"(p));
}
static inline void clflushopt(const volatile void *p)
{
asm volatile ("clflushopt (%0)" :: "r"(p));
}
/* Write the task register */ /* Write the task register */
#define CPU_LTR_EXECUTE(ltr_ptr) \ #define CPU_LTR_EXECUTE(ltr_ptr) \
{ \ { \

22
hypervisor/include/arch/x86/asm/mmu.h
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@ -45,10 +45,8 @@
#ifndef ASSEMBLER #ifndef ASSEMBLER
#include <asm/cpu.h>
#include <asm/page.h> #include <asm/page.h>
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/cpu_caps.h>
/* Define cache line size (in bytes) */ /* Define cache line size (in bytes) */
#define CACHE_LINE_SIZE 64U #define CACHE_LINE_SIZE 64U
@ -196,26 +194,6 @@ void flush_address_space(void *addr, uint64_t size);
*/ */
void invept(const void *eptp); void invept(const void *eptp);
static inline void invlpg(unsigned long addr)
{
asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
}
static inline void cache_flush_invalidate_all(void)
{
asm volatile (" wbinvd\n" : : : "memory");
}
static inline void clflush(const volatile void *p)
{
asm volatile ("clflush (%0)" :: "r"(p));
}
static inline void clflushopt(const volatile void *p)
{
asm volatile ("clflushopt (%0)" :: "r"(p));
}
/* get PDPT address from CR3 vaule in PAE mode */ /* get PDPT address from CR3 vaule in PAE mode */
static inline uint64_t get_pae_pdpt_addr(uint64_t cr3) static inline uint64_t get_pae_pdpt_addr(uint64_t cr3)
{ {