github/acrn-hypervisor
1
0
Fork 0
mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2026-06-08 01:54:44 +00:00
Code Issues Projects Releases Wiki Activity

hv: implement msi.c to handle MSI remapping for vm0

Browse Source 
Emulate MSI Capability structure for vm0 in sharing mode:

- it intercepts the IO requests for MSI Capability structure, emulates
  the Message Control word, and bypasses all other I/O requests to the
  physical device.

- criteria to trigger MSI remapping: MSI Enable bit is being changed,
  Message Data/Addr is being changed when MSI Enable is set.

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
This commit is contained in:
Zide Chen
2018-09-24 12:29:01 -07:00
committed by lijinxia
parent 6af47f249c
commit dcebdb8e98
6 changed files with 271 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
hypervisor/dm/hw/pci.c
View File

@@ -99,6 +99,24 @@ void pci_pdev_write_cfg(union pci_bdf bdf, uint32_t offset, uint32_t bytes, uint
spinlock_release(&pci_device_lock);
}
/* enable: 1: enable INTx; 0: Disable INTx */
void enable_disable_pci_intx(union pci_bdf bdf, bool enable)
{
uint32_t cmd, new_cmd;
/* Set or clear the INTXDIS bit in COMMAND register */
cmd = pci_pdev_read_cfg(bdf, PCIR_COMMAND, 2U);
if (enable) {
new_cmd = cmd & ~PCIM_CMD_INTxDIS;
} else {
new_cmd = cmd | PCIM_CMD_INTxDIS;
}
if ((cmd ^ new_cmd) != 0U) {
pci_pdev_write_cfg(bdf, PCIR_COMMAND, 0x2U, new_cmd);
}
}
#define BUS_SCAN_SKIP 0U
#define BUS_SCAN_PENDING 1U
#define BUS_SCAN_COMPLETE 2U