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hv: support at most MAX_VUART_NUM_PER_VM legacy vuarts

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In the current hypervisor, only support at most two legacy vuarts
(COM1 and COM2) for a VM, COM1 is usually configured as VM console,
COM2 is configured as communication channel of S5 feature.
Hypervisor can support MAX_VUART_NUM_PER_VM(8) legacy vuart, but only
register handlers for two legacy vuart since the assumption (legacy
vuart is less than 2) is made.
In the current hypervisor configurtion, io port (2F8H) is always
allocated for virtual COM2, it will be not friendly if user wants to
assign this port to physical COM2.
Legacy vuart is common communication channel between service VM and
user VM, it can work in polling mode and its driver exits in each
guest OS. The channel can be used to send shutdown command to user VM
in S5 featuare, so need to config serval vuarts for service VM and one
vuart for each user VM.

The following changes will be made to support at most
MAX_VUART_NUM_PER_VM legacy vuarts:
   - Refine legacy vuarts initialization to register PIO handler for
related vuart.
   - Update assumption of legacy vuart number.

BTW, config tools updates about legacy vuarts will be made in other
patch.

v1-->v2:
	Update commit message to make this patch's purpose clearer;
	If vuart index is valid, register handler for it.

Tracked-On: #6652
Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@Intel.com>
This commit is contained in:
Xiangyang Wu 2021-10-03 17:26:54 +08:00 committed by wenlingz
parent ef1b10349b
commit dec8d7e22f
2 changed files with 6 additions and 16 deletions
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17
hypervisor/dm/vuart.c
View File

@ -548,31 +548,22 @@ static bool vuart_read(struct acrn_vcpu *vcpu, uint16_t offset_arg, __unused siz
}
/*
* @pre: vuart_idx = 0 or 1
* @pre: vuart_idx < MAX_VUART_NUM_PER_VM
*/
static bool vuart_register_io_handler(struct acrn_vm *vm, uint16_t port_base, uint32_t vuart_idx)
{
uint32_t pio_idx;
bool ret = true;
struct vm_io_range range = {
.base = port_base,
.len = 8U
};
switch (vuart_idx) {
case 0U:
pio_idx = UART_PIO_IDX0;
break;
case 1U:
pio_idx = UART_PIO_IDX1;
break;
default:
if (vuart_idx < MAX_VUART_NUM_PER_VM) {
register_pio_emulation_handler(vm, UART_PIO_IDX0 + vuart_idx, &range, vuart_read, vuart_write);
} else {
printf("Not support vuart index %d, will not register \n", vuart_idx);
ret = false;
}
if (ret != 0U) {
register_pio_emulation_handler(vm, pio_idx, &range, vuart_read, vuart_write);
}
return ret;
}

5
hypervisor/include/arch/x86/asm/guest/vmx_io.h
View File

@ -15,10 +15,9 @@
#define PIC_ELC_PIO_IDX (PIC_SECONDARY_PIO_IDX + 1U)
#define PCI_CFGADDR_PIO_IDX (PIC_ELC_PIO_IDX + 1U)
#define PCI_CFGDATA_PIO_IDX (PCI_CFGADDR_PIO_IDX + 1U)
/* When MAX_VUART_NUM_PER_VM is larger than 2, UART_PIO_IDXn should also be added here */
/* MAX_VUART_NUM_PER_VM is 8, so allocate UART_PIO_IDX0~UART_PIO_IDX0 + 7 for 8 vuart */
#define UART_PIO_IDX0 (PCI_CFGDATA_PIO_IDX + 1U)
#define UART_PIO_IDX1 (UART_PIO_IDX0 + 1U)
#define PM1A_EVT_PIO_IDX (UART_PIO_IDX1 + 1U)
#define PM1A_EVT_PIO_IDX (UART_PIO_IDX0 + MAX_VUART_NUM_PER_VM)
#define PM1A_CNT_PIO_IDX (PM1A_EVT_PIO_IDX + 1U)
#define PM1B_EVT_PIO_IDX (PM1A_CNT_PIO_IDX + 1U)
#define PM1B_CNT_PIO_IDX (PM1B_EVT_PIO_IDX + 1U)