mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-06-21 05:02:24 +00:00
hv: vmcs: fix MISRA-C violations related to multiple exits
This patch fixes the MISRA-C violations in arch/x86/vmcs.c. * make the function have only one exit point v1 -> v2: * update 'is_cr0_write_valid' and 'is_cr4_write_valid' use `if ... else` rather than check 'ret' value Tracked-On: #861 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Shiqing Gao
wenlingz
parent
4618a6b17d
commit
e283e77424
@ -17,6 +17,7 @@ static uint64_t cr4_always_off_mask;
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bool is_vmx_disabled(void)
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{
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uint64_t msr_val;
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bool ret = false;
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/* Read Feature ControL MSR */
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msr_val = msr_read(MSR_IA32_FEATURE_CONTROL);
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@ -24,9 +25,10 @@ bool is_vmx_disabled(void)
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/* Check if feature control is locked and vmx cannot be enabled */
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if (((msr_val & MSR_IA32_FEATURE_CONTROL_LOCK) != 0U) &&
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((msr_val & MSR_IA32_FEATURE_CONTROL_VMX_NO_SMX) == 0U)) {
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return true;
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ret = true;
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}
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return false;
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return ret;
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}
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static void init_cr0_cr4_host_mask(void)
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@ -96,27 +98,30 @@ int32_t vmx_wrmsr_pat(struct acrn_vcpu *vcpu, uint64_t value)
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{
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uint32_t i;
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uint64_t field;
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int32_t ret = 0;
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for (i = 0U; i < 8U; i++) {
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field = (value >> (i * 8U)) & 0xffUL;
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if (pat_mem_type_invalid(field) ||
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((PAT_FIELD_RSV_BITS & field) != 0UL)) {
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if (pat_mem_type_invalid(field) || ((PAT_FIELD_RSV_BITS & field) != 0UL)) {
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pr_err("invalid guest IA32_PAT: 0x%016llx", value);
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return -EINVAL;
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ret = -EINVAL;
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break;
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}
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}
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vcpu_set_guest_msr(vcpu, MSR_IA32_PAT, value);
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if (ret == 0) {
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vcpu_set_guest_msr(vcpu, MSR_IA32_PAT, value);
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/*
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* If context->cr0.CD is set, we defer any further requests to write
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* guest's IA32_PAT, until the time when guest's CR0.CD is being cleared
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*/
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if ((vcpu_get_cr0(vcpu) & CR0_CD) == 0UL) {
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exec_vmwrite64(VMX_GUEST_IA32_PAT_FULL, value);
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/*
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* If context->cr0.CD is set, we defer any further requests to write
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* guest's IA32_PAT, until the time when guest's CR0.CD is being cleared
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*/
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if ((vcpu_get_cr0(vcpu) & CR0_CD) == 0UL) {
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exec_vmwrite64(VMX_GUEST_IA32_PAT_FULL, value);
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}
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}
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return 0;
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return ret;
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}
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static void load_pdptrs(const struct acrn_vcpu *vcpu)
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@ -135,36 +140,39 @@ static void load_pdptrs(const struct acrn_vcpu *vcpu)
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static bool is_cr0_write_valid(struct acrn_vcpu *vcpu, uint64_t cr0)
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{
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bool ret = true;
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/* Shouldn't set always off bit */
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if ((cr0 & cr0_always_off_mask) != 0UL) {
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return false;
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ret = false;
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} else {
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/* SDM 25.3 "Changes to instruction behavior in VMX non-root"
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*
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* We always require "unrestricted guest" control enabled. So
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*
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* CR0.PG = 1, CR4.PAE = 0 and IA32_EFER.LME = 1 is invalid.
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* CR0.PE = 0 and CR0.PG = 1 is invalid.
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*/
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if (((cr0 & CR0_PG) != 0UL) && (!is_pae(vcpu)) &&
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((vcpu_get_efer(vcpu) & MSR_IA32_EFER_LME_BIT) != 0UL)) {
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ret = false;
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} else {
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if (((cr0 & CR0_PE) == 0UL) && ((cr0 & CR0_PG) != 0UL)) {
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ret = false;
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} else {
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/* SDM 6.15 "Exception and Interrupt Refrerence" GP Exception
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*
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* Loading CR0 register with a set NW flag and a clear CD flag
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* is invalid
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*/
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if (((cr0 & CR0_CD) == 0UL) && ((cr0 & CR0_NW) != 0UL)) {
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ret = false;
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}
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}
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}
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}
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/* SDM 25.3 "Changes to instruction behavior in VMX non-root"
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*
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* We always require "unrestricted guest" control enabled. So
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*
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* CR0.PG = 1, CR4.PAE = 0 and IA32_EFER.LME = 1 is invalid.
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* CR0.PE = 0 and CR0.PG = 1 is invalid.
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*/
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if (((cr0 & CR0_PG) != 0UL) && (!is_pae(vcpu)) && ((vcpu_get_efer(vcpu) & MSR_IA32_EFER_LME_BIT) != 0UL)) {
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return false;
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}
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if (((cr0 & CR0_PE) == 0UL) && ((cr0 & CR0_PG) != 0UL)) {
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return false;
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}
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/* SDM 6.15 "Exception and Interrupt Refrerence" GP Exception
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*
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* Loading CR0 regsiter with a set NW flag and a clear CD flag
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* is invalid
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*/
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if (((cr0 & CR0_CD) == 0UL) && ((cr0 & CR0_NW) != 0UL)) {
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return false;
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}
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return true;
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return ret;
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}
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/*
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@ -199,114 +207,115 @@ void vmx_write_cr0(struct acrn_vcpu *vcpu, uint64_t cr0)
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if (!is_cr0_write_valid(vcpu, cr0)) {
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pr_dbg("Invalid cr0 write operation from guest");
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vcpu_inject_gp(vcpu, 0U);
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return;
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}
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} else {
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/* SDM 2.5
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* When loading a control register, reserved bit should always set
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* to the value previously read.
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*/
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cr0_mask &= ~CR0_RESERVED_MASK;
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/* SDM 2.5
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* When loading a control register, reserved bit should always set
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* to the value previously read.
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*/
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cr0_mask &= ~CR0_RESERVED_MASK;
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if (!old_paging_enabled && ((cr0_mask & CR0_PG) != 0UL)) {
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if ((vcpu_get_efer(vcpu) & MSR_IA32_EFER_LME_BIT) != 0UL) {
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/* Enable long mode */
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pr_dbg("VMM: Enable long mode");
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entry_ctrls = exec_vmread32(VMX_ENTRY_CONTROLS);
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entry_ctrls |= VMX_ENTRY_CTLS_IA32E_MODE;
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exec_vmwrite32(VMX_ENTRY_CONTROLS, entry_ctrls);
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if (!old_paging_enabled && ((cr0_mask & CR0_PG) != 0UL)) {
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if ((vcpu_get_efer(vcpu) & MSR_IA32_EFER_LME_BIT) != 0UL) {
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/* Enable long mode */
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pr_dbg("VMM: Enable long mode");
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entry_ctrls = exec_vmread32(VMX_ENTRY_CONTROLS);
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entry_ctrls |= VMX_ENTRY_CTLS_IA32E_MODE;
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exec_vmwrite32(VMX_ENTRY_CONTROLS, entry_ctrls);
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vcpu_set_efer(vcpu,
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vcpu_get_efer(vcpu) | MSR_IA32_EFER_LMA_BIT);
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} else if (is_pae(vcpu)) {
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/* enabled PAE from paging disabled */
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load_pdptrs(vcpu);
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} else {
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/* do nothing */
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}
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} else if (old_paging_enabled && ((cr0_mask & CR0_PG) == 0UL)) {
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if ((vcpu_get_efer(vcpu) & MSR_IA32_EFER_LME_BIT) != 0UL) {
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/* Disable long mode */
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pr_dbg("VMM: Disable long mode");
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entry_ctrls = exec_vmread32(VMX_ENTRY_CONTROLS);
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entry_ctrls &= ~VMX_ENTRY_CTLS_IA32E_MODE;
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exec_vmwrite32(VMX_ENTRY_CONTROLS, entry_ctrls);
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vcpu_set_efer(vcpu,
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vcpu_get_efer(vcpu) | MSR_IA32_EFER_LMA_BIT);
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} else if (is_pae(vcpu)) {
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/* enabled PAE from paging disabled */
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load_pdptrs(vcpu);
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vcpu_set_efer(vcpu,
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vcpu_get_efer(vcpu) & ~MSR_IA32_EFER_LMA_BIT);
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}
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} else {
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/* do nothing */
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}
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} else if (old_paging_enabled && ((cr0_mask & CR0_PG) == 0UL)) {
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if ((vcpu_get_efer(vcpu) & MSR_IA32_EFER_LME_BIT) != 0UL) {
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/* Disable long mode */
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pr_dbg("VMM: Disable long mode");
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entry_ctrls = exec_vmread32(VMX_ENTRY_CONTROLS);
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entry_ctrls &= ~VMX_ENTRY_CTLS_IA32E_MODE;
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exec_vmwrite32(VMX_ENTRY_CONTROLS, entry_ctrls);
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vcpu_set_efer(vcpu,
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vcpu_get_efer(vcpu) & ~MSR_IA32_EFER_LMA_BIT);
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}
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} else {
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/* do nothing */
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}
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/* If CR0.CD or CR0.NW get cr0_changed_bits */
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if ((cr0_changed_bits & (CR0_CD | CR0_NW)) != 0UL) {
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/* No action if only CR0.NW is cr0_changed_bits */
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if ((cr0_changed_bits & CR0_CD) != 0UL) {
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if ((cr0_mask & CR0_CD) != 0UL) {
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/*
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* When the guest requests to set CR0.CD, we don't allow
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* guest's CR0.CD to be actually set, instead, we write guest
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* IA32_PAT with all-UC entries to emulate the cache
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* disabled behavior
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*/
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exec_vmwrite64(VMX_GUEST_IA32_PAT_FULL, PAT_ALL_UC_VALUE);
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if (!iommu_snoop_supported(vcpu->vm)) {
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cache_flush_invalidate_all();
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/* If CR0.CD or CR0.NW get cr0_changed_bits */
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if ((cr0_changed_bits & (CR0_CD | CR0_NW)) != 0UL) {
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/* No action if only CR0.NW is cr0_changed_bits */
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if ((cr0_changed_bits & CR0_CD) != 0UL) {
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if ((cr0_mask & CR0_CD) != 0UL) {
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/*
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* When the guest requests to set CR0.CD, we don't allow
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* guest's CR0.CD to be actually set, instead, we write guest
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* IA32_PAT with all-UC entries to emulate the cache
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* disabled behavior
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*/
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exec_vmwrite64(VMX_GUEST_IA32_PAT_FULL, PAT_ALL_UC_VALUE);
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if (!iommu_snoop_supported(vcpu->vm)) {
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cache_flush_invalidate_all();
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}
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} else {
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/* Restore IA32_PAT to enable cache again */
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exec_vmwrite64(VMX_GUEST_IA32_PAT_FULL,
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vcpu_get_guest_msr(vcpu, MSR_IA32_PAT));
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}
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} else {
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/* Restore IA32_PAT to enable cache again */
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exec_vmwrite64(VMX_GUEST_IA32_PAT_FULL,
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vcpu_get_guest_msr(vcpu, MSR_IA32_PAT));
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vcpu_make_request(vcpu, ACRN_REQUEST_EPT_FLUSH);
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}
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}
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if ((cr0_changed_bits & (CR0_PG | CR0_WP)) != 0UL) {
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vcpu_make_request(vcpu, ACRN_REQUEST_EPT_FLUSH);
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}
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/* CR0 has no always off bits, except the always on bits, and reserved
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* bits, allow to set according to guest.
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*/
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cr0_vmx = cr0_always_on_mask | cr0_mask;
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/* Don't set CD or NW bit to guest */
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cr0_vmx &= ~(CR0_CD | CR0_NW);
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exec_vmwrite(VMX_GUEST_CR0, cr0_vmx & 0xFFFFFFFFUL);
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exec_vmwrite(VMX_CR0_READ_SHADOW, cr0_mask & 0xFFFFFFFFUL);
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/* clear read cache, next time read should from VMCS */
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bitmap_clear_lock(CPU_REG_CR0, &vcpu->reg_cached);
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pr_dbg("VMM: Try to write %016llx, allow to write 0x%016llx to CR0", cr0_mask, cr0_vmx);
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}
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if ((cr0_changed_bits & (CR0_PG | CR0_WP)) != 0UL) {
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vcpu_make_request(vcpu, ACRN_REQUEST_EPT_FLUSH);
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}
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/* CR0 has no always off bits, except the always on bits, and reserved
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* bits, allow to set according to guest.
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*/
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cr0_vmx = cr0_always_on_mask | cr0_mask;
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/* Don't set CD or NW bit to guest */
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cr0_vmx &= ~(CR0_CD | CR0_NW);
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exec_vmwrite(VMX_GUEST_CR0, cr0_vmx & 0xFFFFFFFFUL);
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exec_vmwrite(VMX_CR0_READ_SHADOW, cr0_mask & 0xFFFFFFFFUL);
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/* clear read cache, next time read should from VMCS */
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bitmap_clear_lock(CPU_REG_CR0, &vcpu->reg_cached);
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pr_dbg("VMM: Try to write %016llx, allow to write 0x%016llx to CR0", cr0_mask, cr0_vmx);
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}
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static bool is_cr4_write_valid(struct acrn_vcpu *vcpu, uint64_t cr4)
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{
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bool ret = true;
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/* Check if guest try to set fixed to 0 bits or reserved bits */
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if ((cr4 & cr4_always_off_mask) != 0U) {
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return false;
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}
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/* Do NOT support nested guest */
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if ((cr4 & CR4_VMXE) != 0UL) {
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return false;
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}
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/* Do NOT support PCID in guest */
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if ((cr4 & CR4_PCIDE) != 0UL) {
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return false;
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}
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if (is_long_mode(vcpu)) {
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if ((cr4 & CR4_PAE) == 0UL) {
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return false;
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ret = false;
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} else {
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/* Do NOT support nested guest */
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if ((cr4 & CR4_VMXE) != 0UL) {
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ret = false;
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} else {
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/* Do NOT support PCID in guest */
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if ((cr4 & CR4_PCIDE) != 0UL) {
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ret = false;
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} else {
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if (is_long_mode(vcpu)) {
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if ((cr4 & CR4_PAE) == 0UL) {
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ret = false;
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}
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}
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}
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}
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}
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return true;
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return ret;
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}
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/*
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@ -352,27 +361,25 @@ void vmx_write_cr4(struct acrn_vcpu *vcpu, uint64_t cr4)
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if (!is_cr4_write_valid(vcpu, cr4)) {
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pr_dbg("Invalid cr4 write operation from guest");
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vcpu_inject_gp(vcpu, 0U);
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return;
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}
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} else {
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if (((cr4 ^ old_cr4) & (CR4_PGE | CR4_PSE | CR4_PAE | CR4_SMEP | CR4_SMAP | CR4_PKE)) != 0UL) {
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if (((cr4 & CR4_PAE) != 0UL) && (is_paging_enabled(vcpu)) && (is_long_mode(vcpu))) {
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load_pdptrs(vcpu);
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}
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if (((cr4 ^ old_cr4) & (CR4_PGE | CR4_PSE | CR4_PAE | CR4_SMEP | CR4_SMAP | CR4_PKE)) != 0UL) {
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if (((cr4 & CR4_PAE) != 0UL) && (is_paging_enabled(vcpu)) && (is_long_mode(vcpu))) {
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load_pdptrs(vcpu);
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vcpu_make_request(vcpu, ACRN_REQUEST_EPT_FLUSH);
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}
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vcpu_make_request(vcpu, ACRN_REQUEST_EPT_FLUSH);
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/* Aways off bits and reserved bits has been filtered above */
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cr4_vmx = cr4_always_on_mask | cr4;
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exec_vmwrite(VMX_GUEST_CR4, cr4_vmx & 0xFFFFFFFFUL);
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exec_vmwrite(VMX_CR4_READ_SHADOW, cr4 & 0xFFFFFFFFUL);
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/* clear read cache, next time read should from VMCS */
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bitmap_clear_lock(CPU_REG_CR4, &vcpu->reg_cached);
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pr_dbg("VMM: Try to write %016llx, allow to write 0x%016llx to CR4", cr4, cr4_vmx);
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}
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/* Aways off bits and reserved bits has been filtered above */
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cr4_vmx = cr4_always_on_mask | cr4;
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exec_vmwrite(VMX_GUEST_CR4, cr4_vmx & 0xFFFFFFFFUL);
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exec_vmwrite(VMX_CR4_READ_SHADOW, cr4 & 0xFFFFFFFFUL);
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/* clear read cache, next time read should from VMCS */
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bitmap_clear_lock(CPU_REG_CR4, &vcpu->reg_cached);
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pr_dbg("VMM: Try to write %016llx, allow to write 0x%016llx to CR4",
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cr4, cr4_vmx);
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}
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/* rip, rsp, ia32_efer and rflags are written to VMCS in start_vcpu */
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