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hv: Let trampoline execution use 1GB pages

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ACRN currently uses 2MB large pages in the page tables setup
for trampoline code and data. This patch lets ACRN use 1GB large
pages instead.
When it comes to fixing symbols in trampoline code, fixing pointers
in PDPT is no more needed as PDPT PTEs contain Physical Address.

Tracked-On: #3899
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This commit is contained in:
Sainath Grandhi
2019-10-08 16:59:51 -07:00
committed by wenlingz
parent 70f2ee398b
commit f01aad7e77
2 changed files with 8 additions and 20 deletions
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9
hypervisor/arch/x86/trampoline.c
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@@ -59,11 +59,13 @@ uint64_t get_trampoline_start16_paddr(void)
return trampoline_start16_paddr;
}
/*
* @pre pcpu_has_cap(X86_FEATURE_PAGE1GB) == true
*/
static void update_trampoline_code_refs(uint64_t dest_pa)
{
void *ptr;
uint64_t val;
int32_t i;
/*
* calculate the fixup CS:IP according to fixup target address
@@ -87,11 +89,6 @@ static void update_trampoline_code_refs(uint64_t dest_pa)
ptr = hpa2hva(dest_pa + trampoline_relo_addr(&cpu_boot_page_tables_start));
*(uint64_t *)(ptr) += dest_pa;
ptr = hpa2hva(dest_pa + trampoline_relo_addr(&trampoline_pdpt_addr));
for (i = 0; i < 4; i++) {
*(uint64_t *)(ptr + sizeof(uint64_t) * i) += dest_pa;
}
/* update the gdt base pointer with relocated offset */
ptr = hpa2hva(dest_pa + trampoline_relo_addr(&trampoline_gdt_ptr));
*(uint64_t *)(ptr + 2) += dest_pa;