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HV: move the ve820 GPU OpRegion address
The ve820 table' hpa1_low area is divided into two parts, which is making the code too complicated and causing problems. Moving the entries that divides the hpa1_low could make things easier. This patch moves the GPU OpRegion to the tail area of 2G, consecutive to the acpi data/nvs area. before: |<---low_1M--->| |<---hpa1_low_part1--->| |<---SSRAM--->| |<---GPU_OpRegion--->| |<---hpa1_low_part2--->| |<---ACPI DATA--->| |<---ACPI NVS--->| ---2G--- after: |<---low_1M--->| |<---hpa1_low_part1--->| |<---SSRAM--->| |<---hpa1_low_part2--->| |<---GPU_OpRegion--->| |<---ACPI DATA--->| |<---ACPI NVS--->| ---2G--- Tracked-On: #6674 Signed-off-by: Zhou, Wu <wu.zhou@intel.com> Reviewed-by: Victor Sun <victor.sun@intel.com> Reviewed-by: Wang, Yu1 <yu1.wang@intel.com>
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@ -15,7 +15,7 @@
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#include <ptdev.h>
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#define ENTRY_HPA1_LOW_PART1 2U
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#define ENTRY_HPA1_LOW_PART2 5U
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#define ENTRY_HPA1_LOW_PART2 4U
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#define ENTRY_HPA1_HI 9U
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static struct e820_entry service_vm_e820[E820_MAX_ENTRIES];
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@ -199,16 +199,16 @@ static const struct e820_entry pre_ve820_template[E820_MAX_ENTRIES] = {
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.length = PRE_RTVM_SW_SRAM_MAX_SIZE,
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.type = E820_TYPE_RESERVED
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},
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{ /* part2 of lowmem of hpa1*/
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.baseaddr = PRE_RTVM_SW_SRAM_BASE_GPA + PRE_RTVM_SW_SRAM_MAX_SIZE,
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.length = GPU_OPREGION_GPA - (PRE_RTVM_SW_SRAM_BASE_GPA + PRE_RTVM_SW_SRAM_MAX_SIZE),
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.type = E820_TYPE_RAM
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},
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{ /* GPU OpRegion for pre-launched VM */
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.baseaddr = GPU_OPREGION_GPA,
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.length = GPU_OPREGION_SIZE,
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.type = E820_TYPE_RESERVED
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},
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{ /* part2 of lowmem of hpa1*/
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.baseaddr = GPU_OPREGION_GPA + GPU_OPREGION_SIZE,
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.length = VIRT_ACPI_DATA_ADDR - (GPU_OPREGION_GPA + GPU_OPREGION_SIZE),
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.type = E820_TYPE_RAM
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},
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{ /* ACPI Reclaim */
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.baseaddr = VIRT_ACPI_DATA_ADDR,/* consecutive from 0x7fe00000UL */
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.length = VIRT_ACPI_DATA_LEN,
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@ -9,6 +9,7 @@
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#include <list.h>
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#include <asm/lib/spinlock.h>
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#include <timer.h>
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#include <vacpi.h>
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enum intx_ctlr {
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@ -20,7 +21,7 @@ enum intx_ctlr {
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#define PTDEV_INTR_INTX (1U << 1U)
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#define GPU_OPREGION_SIZE 0x5000U
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#define GPU_OPREGION_GPA 0x40880000U
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#define GPU_OPREGION_GPA (VIRT_ACPI_DATA_ADDR - GPU_OPREGION_SIZE)
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#define PCIR_ASLS_CTL 0xfcU /* register offset in PCIe configuration space for Opregion base address */
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#define PCIM_ASLS_OPREGION_MASK 0xfffff000U /* opregion need 4KB aligned */
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@ -8,6 +8,7 @@
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#define VACPI_H
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#include <acpi.h>
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#include <asm/guest/vm.h>
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#define ACPI_OEM_ID "ACRN "
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