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HV: mmu: convert hexadecimals used in bitops to unsigned

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Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Junjie Mao 2018-06-19 18:30:40 +08:00 committed by lijinxia
parent 7b548e87db
commit f4bd0798e0
3 changed files with 105 additions and 105 deletions
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18
hypervisor/arch/x86/gdt.c
View File

@ -11,14 +11,14 @@ static void set_tss_desc(union tss_64_descriptor *desc,
{ {
uint32_t u1, u2, u3; uint32_t u1, u2, u3;
u1 = ((uint64_t)tss << 16) & 0xFFFFFFFF; u1 = (uint32_t)(((uint64_t)tss << 16U) & 0xFFFFFFFFU);
u2 = (uint64_t)tss & 0xFF000000; u2 = (uint32_t)((uint64_t)tss & 0xFF000000U);
u3 = ((uint64_t)tss & 0x00FF0000) >> 16; u3 = (uint32_t)(((uint64_t)tss & 0x00FF0000U) >> 16U);
desc->fields.low32.value = u1 | (tss_limit & 0xFFFF); desc->fields.low32.value = u1 | (tss_limit & 0xFFFFU);
desc->fields.base_addr_63_32 = (uint32_t)((uint64_t)tss >> 32); desc->fields.base_addr_63_32 = (uint32_t)((uint64_t)tss >> 32U);
desc->fields.high32.value = (u2 | ((uint32_t)type << 8) | 0x8000 | u3); desc->fields.high32.value = (u2 | ((uint32_t)type << 8U) | 0x8000U | u3);
} }
void load_gdtr_and_tr(void) void load_gdtr_and_tr(void)
@ -28,11 +28,11 @@ void load_gdtr_and_tr(void)
struct tss_64 *tss = &get_cpu_var(tss); struct tss_64 *tss = &get_cpu_var(tss);
/* first entry is not used */ /* first entry is not used */
gdt->rsvd = 0xAAAAAAAAAAAAAAAA; gdt->rsvd = 0xAAAAAAAAAAAAAAAAUL;
/* ring 0 code sel descriptor */ /* ring 0 code sel descriptor */
gdt->host_gdt_code_descriptor.value = 0x00Af9b000000ffff; gdt->host_gdt_code_descriptor.value = 0x00Af9b000000ffffUL;
/* ring 0 data sel descriptor */ /* ring 0 data sel descriptor */
gdt->host_gdt_data_descriptor.value = 0x00cf93000000ffff; gdt->host_gdt_data_descriptor.value = 0x00cf93000000ffffUL;
tss->ist1 = (uint64_t)get_cpu_var(mc_stack) + CONFIG_STACK_SIZE; tss->ist1 = (uint64_t)get_cpu_var(mc_stack) + CONFIG_STACK_SIZE;
tss->ist2 = (uint64_t)get_cpu_var(df_stack) + CONFIG_STACK_SIZE; tss->ist2 = (uint64_t)get_cpu_var(df_stack) + CONFIG_STACK_SIZE;

18
hypervisor/arch/x86/mmu.c
View File

@ -178,12 +178,12 @@ void invept(struct vcpu *vcpu)
struct invept_desc desc = {0}; struct invept_desc desc = {0};
if (cpu_has_vmx_ept_cap(VMX_EPT_INVEPT_SINGLE_CONTEXT)) { if (cpu_has_vmx_ept_cap(VMX_EPT_INVEPT_SINGLE_CONTEXT)) {
desc.eptp = vcpu->vm->arch_vm.nworld_eptp | (3 << 3) | 6; desc.eptp = vcpu->vm->arch_vm.nworld_eptp | (3UL << 3U) | 6UL;
_invept(INVEPT_TYPE_SINGLE_CONTEXT, desc); _invept(INVEPT_TYPE_SINGLE_CONTEXT, desc);
if (vcpu->vm->sworld_control.sworld_enabled && if (vcpu->vm->sworld_control.sworld_enabled &&
vcpu->vm->arch_vm.sworld_eptp) { vcpu->vm->arch_vm.sworld_eptp) {
desc.eptp = vcpu->vm->arch_vm.sworld_eptp desc.eptp = vcpu->vm->arch_vm.sworld_eptp
| (3 << 3) | 6; | (3UL << 3U) | 6UL;
_invept(INVEPT_TYPE_SINGLE_CONTEXT, desc); _invept(INVEPT_TYPE_SINGLE_CONTEXT, desc);
} }
} else if (cpu_has_vmx_ept_cap(VMX_EPT_INVEPT_GLOBAL_CONTEXT)) } else if (cpu_has_vmx_ept_cap(VMX_EPT_INVEPT_GLOBAL_CONTEXT))
@ -990,10 +990,10 @@ static uint64_t break_page_table(struct map_params *map_params, void *paddr,
/* Keep original attribute(here &0x3f) /* Keep original attribute(here &0x3f)
* bit 0(R) bit1(W) bit2(X) bit3~5 MT * bit 0(R) bit1(W) bit2(X) bit3~5 MT
*/ */
attr |= (entry.entry_val & 0x3f); attr |= (entry.entry_val & 0x3fUL);
} else { } else {
/* Keep original attribute(here &0x7f) */ /* Keep original attribute(here &0x7f) */
attr |= (entry.entry_val & 0x7f); attr |= (entry.entry_val & 0x7fUL);
} }
/* write all entries and keep original attr*/ /* write all entries and keep original attr*/
for (i = 0; i < IA32E_NUM_ENTRIES; i++) { for (i = 0; i < IA32E_NUM_ENTRIES; i++) {
@ -1007,7 +1007,7 @@ static uint64_t break_page_table(struct map_params *map_params, void *paddr,
* (here &0x07) * (here &0x07)
*/ */
MEM_WRITE64(entry.entry_base + entry.entry_off, MEM_WRITE64(entry.entry_base + entry.entry_off,
(entry.entry_val & 0x07) | (entry.entry_val & 0x07UL) |
HVA2HPA(sub_tab_addr)); HVA2HPA(sub_tab_addr));
} else { } else {
/* Write the table entry to map this memory, /* Write the table entry to map this memory,
@ -1016,7 +1016,7 @@ static uint64_t break_page_table(struct map_params *map_params, void *paddr,
* bit5(A) bit6(D or Ignore) * bit5(A) bit6(D or Ignore)
*/ */
MEM_WRITE64(entry.entry_base + entry.entry_off, MEM_WRITE64(entry.entry_base + entry.entry_off,
(entry.entry_val & 0x7f) | (entry.entry_val & 0x7fUL) |
HVA2HPA(sub_tab_addr)); HVA2HPA(sub_tab_addr));
} }
} }
@ -1060,9 +1060,9 @@ static int modify_paging(struct map_params *map_params, void *paddr,
* here attr & 0x7, rwx bit0:2 * here attr & 0x7, rwx bit0:2
*/ */
ASSERT(!((map_params->page_table_type == PTT_EPT) && ASSERT(!((map_params->page_table_type == PTT_EPT) &&
(((attr & 0x7) == IA32E_EPT_W_BIT) || (((attr & 0x7UL) == IA32E_EPT_W_BIT) ||
((attr & 0x7) == (IA32E_EPT_W_BIT | IA32E_EPT_X_BIT)) || ((attr & 0x7UL) == (IA32E_EPT_W_BIT | IA32E_EPT_X_BIT)) ||
(((attr & 0x7) == IA32E_EPT_X_BIT) && (((attr & 0x7UL) == IA32E_EPT_X_BIT) &&
!cpu_has_vmx_ept_cap(VMX_EPT_EXECUTE_ONLY)))), !cpu_has_vmx_ept_cap(VMX_EPT_EXECUTE_ONLY)))),
"incorrect memory attribute set!\n"); "incorrect memory attribute set!\n");
/* Loop until the entire block of memory is appropriately /* Loop until the entire block of memory is appropriately

174
hypervisor/include/arch/x86/mmu.h
View File

@ -11,126 +11,126 @@
#define IA32E_COMM_ENTRY_SIZE 8 #define IA32E_COMM_ENTRY_SIZE 8
/* Definitions common for all IA-32e related paging entries */ /* Definitions common for all IA-32e related paging entries */
#define IA32E_COMM_P_BIT 0x0000000000000001 #define IA32E_COMM_P_BIT 0x0000000000000001UL
#define IA32E_COMM_RW_BIT 0x0000000000000002 #define IA32E_COMM_RW_BIT 0x0000000000000002UL
#define IA32E_COMM_US_BIT 0x0000000000000004 #define IA32E_COMM_US_BIT 0x0000000000000004UL
#define IA32E_COMM_PWT_BIT 0x0000000000000008 #define IA32E_COMM_PWT_BIT 0x0000000000000008UL
#define IA32E_COMM_PCD_BIT 0x0000000000000010 #define IA32E_COMM_PCD_BIT 0x0000000000000010UL
#define IA32E_COMM_A_BIT 0x0000000000000020 #define IA32E_COMM_A_BIT 0x0000000000000020UL
#define IA32E_COMM_XD_BIT 0x8000000000000000 #define IA32E_COMM_XD_BIT 0x8000000000000000UL
/* Defines for EPT paging entries */ /* Defines for EPT paging entries */
#define IA32E_EPT_R_BIT 0x0000000000000001 #define IA32E_EPT_R_BIT 0x0000000000000001UL
#define IA32E_EPT_W_BIT 0x0000000000000002 #define IA32E_EPT_W_BIT 0x0000000000000002UL
#define IA32E_EPT_X_BIT 0x0000000000000004 #define IA32E_EPT_X_BIT 0x0000000000000004UL
#define IA32E_EPT_UNCACHED (0<<3) #define IA32E_EPT_UNCACHED (0UL<<3)
#define IA32E_EPT_WC (1<<3) #define IA32E_EPT_WC (1UL<<3)
#define IA32E_EPT_WT (4<<3) #define IA32E_EPT_WT (4UL<<3)
#define IA32E_EPT_WP (5<<3) #define IA32E_EPT_WP (5UL<<3)
#define IA32E_EPT_WB (6<<3) #define IA32E_EPT_WB (6UL<<3)
#define IA32E_EPT_MT_MASK (7<<3) #define IA32E_EPT_MT_MASK (7UL<<3)
#define IA32E_EPT_PAT_IGNORE 0x0000000000000040 #define IA32E_EPT_PAT_IGNORE 0x0000000000000040UL
#define IA32E_EPT_ACCESS_FLAG 0x0000000000000100 #define IA32E_EPT_ACCESS_FLAG 0x0000000000000100UL
#define IA32E_EPT_DIRTY_FLAG 0x0000000000000200 #define IA32E_EPT_DIRTY_FLAG 0x0000000000000200UL
#define IA32E_EPT_SNOOP_CTRL 0x0000000000000800 #define IA32E_EPT_SNOOP_CTRL 0x0000000000000800UL
#define IA32E_EPT_SUPPRESS_VE 0x8000000000000000 #define IA32E_EPT_SUPPRESS_VE 0x8000000000000000UL
/* Definitions common or ignored for all IA-32e related paging entries */ /* Definitions common or ignored for all IA-32e related paging entries */
#define IA32E_COMM_D_BIT 0x0000000000000040 #define IA32E_COMM_D_BIT 0x0000000000000040UL
#define IA32E_COMM_G_BIT 0x0000000000000100 #define IA32E_COMM_G_BIT 0x0000000000000100UL
/* Definitions exclusive to a Page Map Level 4 Entry (PML4E) */ /* Definitions exclusive to a Page Map Level 4 Entry (PML4E) */
#define IA32E_PML4E_INDEX_MASK_START 39 #define IA32E_PML4E_INDEX_MASK_START 39
#define IA32E_PML4E_ADDR_MASK 0x0000FF8000000000 #define IA32E_PML4E_ADDR_MASK 0x0000FF8000000000UL
/* Definitions exclusive to a Page Directory Pointer Table Entry (PDPTE) */ /* Definitions exclusive to a Page Directory Pointer Table Entry (PDPTE) */
#define IA32E_PDPTE_D_BIT 0x0000000000000040 #define IA32E_PDPTE_D_BIT 0x0000000000000040UL
#define IA32E_PDPTE_PS_BIT 0x0000000000000080 #define IA32E_PDPTE_PS_BIT 0x0000000000000080UL
#define IA32E_PDPTE_PAT_BIT 0x0000000000001000 #define IA32E_PDPTE_PAT_BIT 0x0000000000001000UL
#define IA32E_PDPTE_ADDR_MASK 0x0000FFFFC0000000 #define IA32E_PDPTE_ADDR_MASK 0x0000FFFFC0000000UL
#define IA32E_PDPTE_INDEX_MASK_START \ #define IA32E_PDPTE_INDEX_MASK_START \
(IA32E_PML4E_INDEX_MASK_START - IA32E_INDEX_MASK_BITS) (IA32E_PML4E_INDEX_MASK_START - IA32E_INDEX_MASK_BITS)
/* Definitions exclusive to a Page Directory Entry (PDE) 1G or 2M */ /* Definitions exclusive to a Page Directory Entry (PDE) 1G or 2M */
#define IA32E_PDE_D_BIT 0x0000000000000040 #define IA32E_PDE_D_BIT 0x0000000000000040UL
#define IA32E_PDE_PS_BIT 0x0000000000000080 #define IA32E_PDE_PS_BIT 0x0000000000000080UL
#define IA32E_PDE_PAT_BIT 0x0000000000001000 #define IA32E_PDE_PAT_BIT 0x0000000000001000UL
#define IA32E_PDE_ADDR_MASK 0x0000FFFFFFE00000 #define IA32E_PDE_ADDR_MASK 0x0000FFFFFFE00000UL
#define IA32E_PDE_INDEX_MASK_START \ #define IA32E_PDE_INDEX_MASK_START \
(IA32E_PDPTE_INDEX_MASK_START - IA32E_INDEX_MASK_BITS) (IA32E_PDPTE_INDEX_MASK_START - IA32E_INDEX_MASK_BITS)
/* Definitions exclusive to Page Table Entries (PTE) */ /* Definitions exclusive to Page Table Entries (PTE) */
#define IA32E_PTE_D_BIT 0x0000000000000040 #define IA32E_PTE_D_BIT 0x0000000000000040UL
#define IA32E_PTE_PAT_BIT 0x0000000000000080 #define IA32E_PTE_PAT_BIT 0x0000000000000080UL
#define IA32E_PTE_G_BIT 0x0000000000000100 #define IA32E_PTE_G_BIT 0x0000000000000100UL
#define IA32E_PTE_ADDR_MASK 0x0000FFFFFFFFF000 #define IA32E_PTE_ADDR_MASK 0x0000FFFFFFFFF000UL
#define IA32E_PTE_INDEX_MASK_START \ #define IA32E_PTE_INDEX_MASK_START \
(IA32E_PDE_INDEX_MASK_START - IA32E_INDEX_MASK_BITS) (IA32E_PDE_INDEX_MASK_START - IA32E_INDEX_MASK_BITS)
/** The 'Present' bit in a 32 bit paging page directory entry */ /** The 'Present' bit in a 32 bit paging page directory entry */
#define MMU_32BIT_PDE_P 0x00000001 #define MMU_32BIT_PDE_P 0x00000001U
/** The 'Read/Write' bit in a 32 bit paging page directory entry */ /** The 'Read/Write' bit in a 32 bit paging page directory entry */
#define MMU_32BIT_PDE_RW 0x00000002 #define MMU_32BIT_PDE_RW 0x00000002U
/** The 'User/Supervisor' bit in a 32 bit paging page directory entry */ /** The 'User/Supervisor' bit in a 32 bit paging page directory entry */
#define MMU_32BIT_PDE_US 0x00000004 #define MMU_32BIT_PDE_US 0x00000004U
/** The 'Page Write Through' bit in a 32 bit paging page directory entry */ /** The 'Page Write Through' bit in a 32 bit paging page directory entry */
#define MMU_32BIT_PDE_PWT 0x00000008 #define MMU_32BIT_PDE_PWT 0x00000008U
/** The 'Page Cache Disable' bit in a 32 bit paging page directory entry */ /** The 'Page Cache Disable' bit in a 32 bit paging page directory entry */
#define MMU_32BIT_PDE_PCD 0x00000010 #define MMU_32BIT_PDE_PCD 0x00000010U
/** The 'Accessed' bit in a 32 bit paging page directory entry */ /** The 'Accessed' bit in a 32 bit paging page directory entry */
#define MMU_32BIT_PDE_A 0x00000020 #define MMU_32BIT_PDE_A 0x00000020U
/** The 'Dirty' bit in a 32 bit paging page directory entry */ /** The 'Dirty' bit in a 32 bit paging page directory entry */
#define MMU_32BIT_PDE_D 0x00000040 #define MMU_32BIT_PDE_D 0x00000040U
/** The 'Page Size' bit in a 32 bit paging page directory entry */ /** The 'Page Size' bit in a 32 bit paging page directory entry */
#define MMU_32BIT_PDE_PS 0x00000080 #define MMU_32BIT_PDE_PS 0x00000080U
/** The 'Global' bit in a 32 bit paging page directory entry */ /** The 'Global' bit in a 32 bit paging page directory entry */
#define MMU_32BIT_PDE_G 0x00000100 #define MMU_32BIT_PDE_G 0x00000100U
/** The 'PAT' bit in a page 32 bit paging directory entry */ /** The 'PAT' bit in a page 32 bit paging directory entry */
#define MMU_32BIT_PDE_PAT 0x00001000 #define MMU_32BIT_PDE_PAT 0x00001000U
/** The flag that indicates that the page fault was caused by a non present /** The flag that indicates that the page fault was caused by a non present
* page. * page.
*/ */
#define PAGE_FAULT_P_FLAG 0x00000001 #define PAGE_FAULT_P_FLAG 0x00000001U
/** The flag that indicates that the page fault was caused by a write access. */ /** The flag that indicates that the page fault was caused by a write access. */
#define PAGE_FAULT_WR_FLAG 0x00000002 #define PAGE_FAULT_WR_FLAG 0x00000002U
/** The flag that indicates that the page fault was caused in user mode. */ /** The flag that indicates that the page fault was caused in user mode. */
#define PAGE_FAULT_US_FLAG 0x00000004 #define PAGE_FAULT_US_FLAG 0x00000004U
/** The flag that indicates that the page fault was caused by a reserved bit /** The flag that indicates that the page fault was caused by a reserved bit
* violation. * violation.
*/ */
#define PAGE_FAULT_RSVD_FLAG 0x00000008 #define PAGE_FAULT_RSVD_FLAG 0x00000008U
/** The flag that indicates that the page fault was caused by an instruction /** The flag that indicates that the page fault was caused by an instruction
* fetch. * fetch.
*/ */
#define PAGE_FAULT_ID_FLAG 0x00000010 #define PAGE_FAULT_ID_FLAG 0x00000010U
/* Defines used for common memory sizes */ /* Defines used for common memory sizes */
#define MEM_1K 1024UL #define MEM_1K 1024U
#define MEM_2K (MEM_1K * 2UL) #define MEM_2K (MEM_1K * 2U)
#define MEM_4K (MEM_1K * 4UL) #define MEM_4K (MEM_1K * 4U)
#define MEM_8K (MEM_1K * 8UL) #define MEM_8K (MEM_1K * 8U)
#define MEM_16K (MEM_1K * 16UL) #define MEM_16K (MEM_1K * 16U)
#define MEM_32K (MEM_1K * 32UL) #define MEM_32K (MEM_1K * 32U)
#define MEM_64K (MEM_1K * 64UL) #define MEM_64K (MEM_1K * 64U)
#define MEM_128K (MEM_1K * 128UL) #define MEM_128K (MEM_1K * 128U)
#define MEM_256K (MEM_1K * 256UL) #define MEM_256K (MEM_1K * 256U)
#define MEM_512K (MEM_1K * 512UL) #define MEM_512K (MEM_1K * 512U)
#define MEM_1M (MEM_1K * 1024UL) #define MEM_1M (MEM_1K * 1024U)
#define MEM_2M (MEM_1M * 2UL) #define MEM_2M (MEM_1M * 2U)
#define MEM_4M (MEM_1M * 4UL) #define MEM_4M (MEM_1M * 4U)
#define MEM_8M (MEM_1M * 8UL) #define MEM_8M (MEM_1M * 8U)
#define MEM_16M (MEM_1M * 16UL) #define MEM_16M (MEM_1M * 16U)
#define MEM_32M (MEM_1M * 32UL) #define MEM_32M (MEM_1M * 32U)
#define MEM_64M (MEM_1M * 64UL) #define MEM_64M (MEM_1M * 64U)
#define MEM_128M (MEM_1M * 128UL) #define MEM_128M (MEM_1M * 128U)
#define MEM_256M (MEM_1M * 256UL) #define MEM_256M (MEM_1M * 256U)
#define MEM_512M (MEM_1M * 512UL) #define MEM_512M (MEM_1M * 512U)
#define MEM_1G (MEM_1M * 1024UL) #define MEM_1G (MEM_1M * 1024U)
#define MEM_2G (MEM_1G * 2UL) #define MEM_2G (MEM_1G * 2U)
#define MEM_3G (MEM_1G * 3UL) #define MEM_3G (MEM_1G * 3U)
#define MEM_4G (MEM_1G * 4UL) #define MEM_4G (MEM_1G * 4U)
#define MEM_5G (MEM_1G * 5UL) #define MEM_5G (MEM_1G * 5U)
#define MEM_6G (MEM_1G * 6UL) #define MEM_6G (MEM_1G * 6U)
#ifndef ASSEMBLER #ifndef ASSEMBLER
@ -184,15 +184,15 @@
*/ */
/* Generic memory attributes */ /* Generic memory attributes */
#define MMU_MEM_ATTR_READ 0x00000001 #define MMU_MEM_ATTR_READ 0x00000001U
#define MMU_MEM_ATTR_WRITE 0x00000002 #define MMU_MEM_ATTR_WRITE 0x00000002U
#define MMU_MEM_ATTR_EXECUTE 0x00000004 #define MMU_MEM_ATTR_EXECUTE 0x00000004U
#define MMU_MEM_ATTR_USER 0x00000008 #define MMU_MEM_ATTR_USER 0x00000008U
#define MMU_MEM_ATTR_WB_CACHE 0x00000040 #define MMU_MEM_ATTR_WB_CACHE 0x00000040U
#define MMU_MEM_ATTR_WT_CACHE 0x00000080 #define MMU_MEM_ATTR_WT_CACHE 0x00000080U
#define MMU_MEM_ATTR_UNCACHED 0x00000100 #define MMU_MEM_ATTR_UNCACHED 0x00000100U
#define MMU_MEM_ATTR_WC 0x00000200 #define MMU_MEM_ATTR_WC 0x00000200U
#define MMU_MEM_ATTR_WP 0x00000400 #define MMU_MEM_ATTR_WP 0x00000400U
/* Definitions for memory types related to x64 */ /* Definitions for memory types related to x64 */
#define MMU_MEM_ATTR_BIT_READ_WRITE IA32E_COMM_RW_BIT #define MMU_MEM_ATTR_BIT_READ_WRITE IA32E_COMM_RW_BIT
@ -203,7 +203,7 @@
* encoding. See also pat.h * encoding. See also pat.h
*/ */
/* Selects PAT0 WB */ /* Selects PAT0 WB */
#define MMU_MEM_ATTR_TYPE_CACHED_WB (0x0000000000000000) #define MMU_MEM_ATTR_TYPE_CACHED_WB (0x0000000000000000UL)
/* Selects PAT1 WT */ /* Selects PAT1 WT */
#define MMU_MEM_ATTR_TYPE_CACHED_WT (IA32E_COMM_PWT_BIT) #define MMU_MEM_ATTR_TYPE_CACHED_WT (IA32E_COMM_PWT_BIT)
/* Selects PAT2 UCM */ /* Selects PAT2 UCM */