mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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HV: cpu: convert hexadecimals used in bitops to unsigned
Per MISRA C, operands to bit-wise operations should have unsigned
types. However, C99 prioritizes to use signed integers for hexadecimal constants
without the 'U' suffixes, leading to tons of bit operations on signed integers.
This patch series add the 'U' suffixes to the constants which are used in bit
operations, and add the intended width of these integers when applicable
(i.e. the target value is at least 32-bit wide) to avoid functional differences
due to signed vs. unsigned extensions. The rule of thumb is:
'0' for signed char/short/int
'0U' for unsigned char/short/int
'0L' for signed long (should be 64-bit)
'0UL' for unsigned long (should be 64-bit)
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This commit is contained in:
Junjie Mao
lijinxia
parent
5aca8b1cdd
commit
7b548e87db
@ -34,12 +34,12 @@ uint64_t trampoline_start16_paddr;
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/* TODO: add more capability per requirement */
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/*APICv features*/
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#define VAPIC_FEATURE_VIRT_ACCESS (1 << 0)
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#define VAPIC_FEATURE_VIRT_REG (1 << 1)
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#define VAPIC_FEATURE_INTR_DELIVERY (1 << 2)
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#define VAPIC_FEATURE_TPR_SHADOW (1 << 3)
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#define VAPIC_FEATURE_POST_INTR (1 << 4)
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#define VAPIC_FEATURE_VX2APIC_MODE (1 << 5)
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#define VAPIC_FEATURE_VIRT_ACCESS (1U << 0)
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#define VAPIC_FEATURE_VIRT_REG (1U << 1)
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#define VAPIC_FEATURE_INTR_DELIVERY (1U << 2)
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#define VAPIC_FEATURE_TPR_SHADOW (1U << 3)
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#define VAPIC_FEATURE_POST_INTR (1U << 4)
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#define VAPIC_FEATURE_VX2APIC_MODE (1U << 5)
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struct cpu_capability {
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uint8_t vapic_features;
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@ -59,7 +59,7 @@ int ibrs_type;
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inline bool cpu_has_cap(uint32_t bit)
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{
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int feat_idx = bit >> 5;
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int feat_bit = bit & 0x1f;
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int feat_bit = bit & 0x1fU;
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if (feat_idx >= FEATURE_WORDS)
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return false;
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@ -83,7 +83,7 @@ static inline bool get_monitor_cap(void)
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static uint64_t get_address_mask(uint8_t limit)
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{
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return ((1ULL << limit) - 1) & CPU_PAGE_MASK;
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return ((1UL << limit) - 1UL) & CPU_PAGE_MASK;
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}
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static void get_cpu_capabilities(void)
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@ -98,14 +98,14 @@ static void get_cpu_capabilities(void)
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cpuid(CPUID_FEATURES, &eax, &unused,
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&boot_cpu_data.cpuid_leaves[FEAT_1_ECX],
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&boot_cpu_data.cpuid_leaves[FEAT_1_EDX]);
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family = (eax >> 8) & 0xff;
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if (family == 0xF)
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family += (eax >> 20) & 0xff;
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family = (eax >> 8) & 0xffU;
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if (family == 0xFU)
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family += (eax >> 20) & 0xffU;
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boot_cpu_data.x86 = family;
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model = (eax >> 4) & 0xf;
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if (family >= 0x06)
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model += ((eax >> 16) & 0xf) << 4;
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model = (eax >> 4) & 0xfU;
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if (family >= 0x06U)
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model += ((eax >> 16) & 0xfU) << 4;
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boot_cpu_data.x86_model = model;
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@ -131,8 +131,8 @@ static void get_cpu_capabilities(void)
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/* EAX bits 07-00: #Physical Address Bits
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* bits 15-08: #Linear Address Bits
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*/
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boot_cpu_data.x86_virt_bits = (eax >> 8) & 0xff;
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boot_cpu_data.x86_phys_bits = eax & 0xff;
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boot_cpu_data.x86_virt_bits = (eax >> 8) & 0xffU;
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boot_cpu_data.x86_phys_bits = eax & 0xffU;
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boot_cpu_data.physical_address_mask =
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get_address_mask(boot_cpu_data.x86_phys_bits);
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}
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@ -629,10 +629,10 @@ static void update_trampoline_code_refs(uint64_t dest_pa)
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val = dest_pa + (uint64_t)trampoline_fixup_target;
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ptr = HPA2HVA(dest_pa + (uint64_t)trampoline_fixup_cs);
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*(uint16_t *)(ptr) = (uint16_t)(val >> 4) & 0xFFFF;
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*(uint16_t *)(ptr) = (uint16_t)(val >> 4) & 0xFFFFU;
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ptr = HPA2HVA(dest_pa + (uint64_t)trampoline_fixup_ip);
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*(uint16_t *)(ptr) = (uint16_t)(val & 0xf);
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*(uint16_t *)(ptr) = (uint16_t)(val & 0xfU);
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/* Update temporary page tables */
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ptr = HPA2HVA(dest_pa + (uint64_t)CPU_Boot_Page_Tables_ptr);
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@ -182,7 +182,7 @@ int set_vcpuid_entries(struct vm *vm)
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if (result != 0)
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return result;
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times = entry.eax & 0xff;
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times = entry.eax & 0xffUL;
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for (j = 1; j < times; j++) {
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init_vcpuid_entry(vm, i, j,
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CPUID_CHECK_SUBLEAF, &entry);
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@ -41,80 +41,80 @@
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/* Define page size */
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#define CPU_PAGE_SHIFT 12
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#define CPU_PAGE_SIZE 0x1000
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#define CPU_PAGE_MASK 0xFFFFFFFFFFFFF000
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#define CPU_PAGE_MASK 0xFFFFFFFFFFFFF000UL
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#define MMU_PTE_PAGE_SHIFT CPU_PAGE_SHIFT
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#define MMU_PDE_PAGE_SHIFT 21
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/* Define CPU stack alignment */
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#define CPU_STACK_ALIGN 16
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#define CPU_STACK_ALIGN 16UL
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/* CR0 register definitions */
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#define CR0_PG (1<<31) /* paging enable */
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#define CR0_CD (1<<30) /* cache disable */
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#define CR0_NW (1<<29) /* not write through */
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#define CR0_AM (1<<18) /* alignment mask */
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#define CR0_WP (1<<16) /* write protect */
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#define CR0_NE (1<<5) /* numeric error */
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#define CR0_ET (1<<4) /* extension type */
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#define CR0_TS (1<<3) /* task switched */
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#define CR0_EM (1<<2) /* emulation */
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#define CR0_MP (1<<1) /* monitor coprocessor */
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#define CR0_PE (1<<0) /* protected mode enabled */
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#define CR0_PG (1U<<31) /* paging enable */
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#define CR0_CD (1U<<30) /* cache disable */
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#define CR0_NW (1U<<29) /* not write through */
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#define CR0_AM (1U<<18) /* alignment mask */
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#define CR0_WP (1U<<16) /* write protect */
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#define CR0_NE (1U<<5) /* numeric error */
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#define CR0_ET (1U<<4) /* extension type */
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#define CR0_TS (1U<<3) /* task switched */
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#define CR0_EM (1U<<2) /* emulation */
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#define CR0_MP (1U<<1) /* monitor coprocessor */
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#define CR0_PE (1U<<0) /* protected mode enabled */
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/* CR3 register definitions */
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#define CR3_PWT (1<<3) /* page-level write through */
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#define CR3_PCD (1<<4) /* page-level cache disable */
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#define CR3_PWT (1U<<3) /* page-level write through */
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#define CR3_PCD (1U<<4) /* page-level cache disable */
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/* CR4 register definitions */
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#define CR4_VME (1<<0) /* virtual 8086 mode extensions */
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#define CR4_PVI (1<<1) /* protected mode virtual interrupts */
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#define CR4_TSD (1<<2) /* time stamp disable */
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#define CR4_DE (1<<3) /* debugging extensions */
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#define CR4_PSE (1<<4) /* page size extensions */
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#define CR4_PAE (1<<5) /* physical address extensions */
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#define CR4_MCE (1<<6) /* machine check enable */
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#define CR4_PGE (1<<7) /* page global enable */
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#define CR4_PCE (1<<8)
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#define CR4_VME (1U<<0) /* virtual 8086 mode extensions */
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#define CR4_PVI (1U<<1) /* protected mode virtual interrupts */
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#define CR4_TSD (1U<<2) /* time stamp disable */
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#define CR4_DE (1U<<3) /* debugging extensions */
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#define CR4_PSE (1U<<4) /* page size extensions */
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#define CR4_PAE (1U<<5) /* physical address extensions */
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#define CR4_MCE (1U<<6) /* machine check enable */
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#define CR4_PGE (1U<<7) /* page global enable */
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#define CR4_PCE (1U<<8)
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/* performance monitoring counter enable */
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#define CR4_OSFXSR (1<<9) /* OS support for FXSAVE/FXRSTOR */
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#define CR4_OSXMMEXCPT (1<<10)
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#define CR4_OSFXSR (1U<<9) /* OS support for FXSAVE/FXRSTOR */
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#define CR4_OSXMMEXCPT (1U<<10)
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/* OS support for unmasked SIMD floating point exceptions */
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#define CR4_VMXE (1<<13) /* VMX enable */
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#define CR4_SMXE (1<<14) /* SMX enable */
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#define CR4_PCIDE (1<<17) /* PCID enable */
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#define CR4_OSXSAVE (1<<18)
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#define CR4_SMEP (1<<20)
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#define CR4_SMAP (1<<21)
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#define CR4_VMXE (1U<<13) /* VMX enable */
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#define CR4_SMXE (1U<<14) /* SMX enable */
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#define CR4_PCIDE (1U<<17) /* PCID enable */
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#define CR4_OSXSAVE (1U<<18)
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#define CR4_SMEP (1U<<20)
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#define CR4_SMAP (1U<<21)
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/* XSAVE and Processor Extended States enable bit */
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/*
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* Entries in the Interrupt Descriptor Table (IDT)
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*/
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#define IDT_DE 0 /* #DE: Divide Error */
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#define IDT_DB 1 /* #DB: Debug */
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#define IDT_NMI 2 /* Nonmaskable External Interrupt */
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#define IDT_BP 3 /* #BP: Breakpoint */
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#define IDT_OF 4 /* #OF: Overflow */
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#define IDT_BR 5 /* #BR: Bound Range Exceeded */
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#define IDT_UD 6 /* #UD: Undefined/Invalid Opcode */
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#define IDT_NM 7 /* #NM: No Math Coprocessor */
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#define IDT_DF 8 /* #DF: Double Fault */
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#define IDT_FPUGP 9 /* Coprocessor Segment Overrun */
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#define IDT_TS 10 /* #TS: Invalid TSS */
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#define IDT_NP 11 /* #NP: Segment Not Present */
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#define IDT_SS 12 /* #SS: Stack Segment Fault */
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#define IDT_GP 13 /* #GP: General Protection Fault */
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#define IDT_PF 14 /* #PF: Page Fault */
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#define IDT_MF 16 /* #MF: FPU Floating-Point Error */
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#define IDT_AC 17 /* #AC: Alignment Check */
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#define IDT_MC 18 /* #MC: Machine Check */
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#define IDT_XF 19 /* #XF: SIMD Floating-Point Exception */
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#define IDT_VE 20 /* #VE: Virtualization Exception */
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#define IDT_DE 0U /* #DE: Divide Error */
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#define IDT_DB 1U /* #DB: Debug */
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#define IDT_NMI 2U /* Nonmaskable External Interrupt */
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#define IDT_BP 3U /* #BP: Breakpoint */
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#define IDT_OF 4U /* #OF: Overflow */
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#define IDT_BR 5U /* #BR: Bound Range Exceeded */
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#define IDT_UD 6U /* #UD: Undefined/Invalid Opcode */
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#define IDT_NM 7U /* #NM: No Math Coprocessor */
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#define IDT_DF 8U /* #DF: Double Fault */
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#define IDT_FPUGP 9U /* Coprocessor Segment Overrun */
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#define IDT_TS 10U /* #TS: Invalid TSS */
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#define IDT_NP 11U /* #NP: Segment Not Present */
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#define IDT_SS 12U /* #SS: Stack Segment Fault */
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#define IDT_GP 13U /* #GP: General Protection Fault */
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#define IDT_PF 14U /* #PF: Page Fault */
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#define IDT_MF 16U /* #MF: FPU Floating-Point Error */
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#define IDT_AC 17U /* #AC: Alignment Check */
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#define IDT_MC 18U /* #MC: Machine Check */
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#define IDT_XF 19U /* #XF: SIMD Floating-Point Exception */
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#define IDT_VE 20U /* #VE: Virtualization Exception */
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/*Bits in EFER special registers */
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#define EFER_LMA 0x000000400 /* Long mode active (R) */
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#define EFER_LMA 0x00000400U /* Long mode active (R) */
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/* CPU clock frequencies (FSB) */
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#define CPU_FSB_83KHZ 83200
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@ -140,7 +140,7 @@
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#define CPU_STATE_DEAD 4
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/* hypervisor stack bottom magic('intl') */
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#define SP_BOTTOM_MAGIC 0x696e746c
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#define SP_BOTTOM_MAGIC 0x696e746cUL
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/* type of speculation control
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* 0 - no speculation control support
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@ -310,7 +310,7 @@ void start_cpus();
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/* This macro writes the stack pointer. */
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#define CPU_SP_WRITE(stack_ptr) \
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{ \
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uint64_t rsp = (uint64_t)stack_ptr & ~(CPU_STACK_ALIGN - 1); \
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uint64_t rsp = (uint64_t)stack_ptr & ~(CPU_STACK_ALIGN - 1UL); \
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asm volatile ("movq %0, %%rsp" : : "r"(rsp)); \
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}
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@ -15,73 +15,73 @@
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#define CPUID_H_
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/* CPUID bit definitions */
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#define CPUID_ECX_SSE3 (1<<0)
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#define CPUID_ECX_PCLMUL (1<<1)
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#define CPUID_ECX_DTES64 (1<<2)
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#define CPUID_ECX_MONITOR (1<<3)
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#define CPUID_ECX_DS_CPL (1<<4)
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#define CPUID_ECX_VMX (1<<5)
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#define CPUID_ECX_SMX (1<<6)
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#define CPUID_ECX_EST (1<<7)
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#define CPUID_ECX_TM2 (1<<8)
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#define CPUID_ECX_SSSE3 (1<<9)
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#define CPUID_ECX_CID (1<<10)
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#define CPUID_ECX_FMA (1<<12)
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#define CPUID_ECX_CX16 (1<<13)
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#define CPUID_ECX_ETPRD (1<<14)
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#define CPUID_ECX_PDCM (1<<15)
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#define CPUID_ECX_DCA (1<<18)
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#define CPUID_ECX_SSE4_1 (1<<19)
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#define CPUID_ECX_SSE4_2 (1<<20)
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#define CPUID_ECX_x2APIC (1<<21)
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#define CPUID_ECX_MOVBE (1<<22)
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#define CPUID_ECX_POPCNT (1<<23)
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#define CPUID_ECX_AES (1<<25)
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#define CPUID_ECX_XSAVE (1<<26)
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#define CPUID_ECX_OSXSAVE (1<<27)
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#define CPUID_ECX_AVX (1<<28)
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#define CPUID_EDX_FPU (1<<0)
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#define CPUID_EDX_VME (1<<1)
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#define CPUID_EDX_DE (1<<2)
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#define CPUID_EDX_PSE (1<<3)
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#define CPUID_EDX_TSC (1<<4)
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#define CPUID_EDX_MSR (1<<5)
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#define CPUID_EDX_PAE (1<<6)
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#define CPUID_EDX_MCE (1<<7)
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#define CPUID_EDX_CX8 (1<<8)
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#define CPUID_EDX_APIC (1<<9)
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#define CPUID_EDX_SEP (1<<11)
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#define CPUID_EDX_MTRR (1<<12)
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#define CPUID_EDX_PGE (1<<13)
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#define CPUID_EDX_MCA (1<<14)
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#define CPUID_EDX_CMOV (1<<15)
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#define CPUID_EDX_PAT (1<<16)
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#define CPUID_EDX_PSE36 (1<<17)
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#define CPUID_EDX_PSN (1<<18)
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#define CPUID_EDX_CLF (1<<19)
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#define CPUID_EDX_DTES (1<<21)
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#define CPUID_EDX_ACPI (1<<22)
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#define CPUID_EDX_MMX (1<<23)
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#define CPUID_EDX_FXSR (1<<24)
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#define CPUID_EDX_SSE (1<<25)
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#define CPUID_EDX_SSE2 (1<<26)
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#define CPUID_EDX_SS (1<<27)
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#define CPUID_EDX_HTT (1<<28)
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#define CPUID_EDX_TM1 (1<<29)
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#define CPUID_EDX_IA64 (1<<30)
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#define CPUID_EDX_PBE (1<<31)
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#define CPUID_ECX_SSE3 (1UL<<0)
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#define CPUID_ECX_PCLMUL (1UL<<1)
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#define CPUID_ECX_DTES64 (1UL<<2)
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#define CPUID_ECX_MONITOR (1UL<<3)
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#define CPUID_ECX_DS_CPL (1UL<<4)
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#define CPUID_ECX_VMX (1UL<<5)
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#define CPUID_ECX_SMX (1UL<<6)
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#define CPUID_ECX_EST (1UL<<7)
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#define CPUID_ECX_TM2 (1UL<<8)
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#define CPUID_ECX_SSSE3 (1UL<<9)
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#define CPUID_ECX_CID (1UL<<10)
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#define CPUID_ECX_FMA (1UL<<12)
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#define CPUID_ECX_CX16 (1UL<<13)
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#define CPUID_ECX_ETPRD (1UL<<14)
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#define CPUID_ECX_PDCM (1UL<<15)
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#define CPUID_ECX_DCA (1UL<<18)
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#define CPUID_ECX_SSE4_1 (1UL<<19)
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#define CPUID_ECX_SSE4_2 (1UL<<20)
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#define CPUID_ECX_x2APIC (1UL<<21)
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#define CPUID_ECX_MOVBE (1UL<<22)
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#define CPUID_ECX_POPCNT (1UL<<23)
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#define CPUID_ECX_AES (1UL<<25)
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#define CPUID_ECX_XSAVE (1UL<<26)
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#define CPUID_ECX_OSXSAVE (1UL<<27)
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#define CPUID_ECX_AVX (1UL<<28)
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#define CPUID_EDX_FPU (1UL<<0)
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#define CPUID_EDX_VME (1UL<<1)
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#define CPUID_EDX_DE (1UL<<2)
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#define CPUID_EDX_PSE (1UL<<3)
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#define CPUID_EDX_TSC (1UL<<4)
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#define CPUID_EDX_MSR (1UL<<5)
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#define CPUID_EDX_PAE (1UL<<6)
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#define CPUID_EDX_MCE (1UL<<7)
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#define CPUID_EDX_CX8 (1UL<<8)
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#define CPUID_EDX_APIC (1UL<<9)
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#define CPUID_EDX_SEP (1UL<<11)
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#define CPUID_EDX_MTRR (1UL<<12)
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#define CPUID_EDX_PGE (1UL<<13)
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#define CPUID_EDX_MCA (1UL<<14)
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#define CPUID_EDX_CMOV (1UL<<15)
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#define CPUID_EDX_PAT (1UL<<16)
|
||||
#define CPUID_EDX_PSE36 (1UL<<17)
|
||||
#define CPUID_EDX_PSN (1UL<<18)
|
||||
#define CPUID_EDX_CLF (1UL<<19)
|
||||
#define CPUID_EDX_DTES (1UL<<21)
|
||||
#define CPUID_EDX_ACPI (1UL<<22)
|
||||
#define CPUID_EDX_MMX (1UL<<23)
|
||||
#define CPUID_EDX_FXSR (1UL<<24)
|
||||
#define CPUID_EDX_SSE (1UL<<25)
|
||||
#define CPUID_EDX_SSE2 (1UL<<26)
|
||||
#define CPUID_EDX_SS (1UL<<27)
|
||||
#define CPUID_EDX_HTT (1UL<<28)
|
||||
#define CPUID_EDX_TM1 (1UL<<29)
|
||||
#define CPUID_EDX_IA64 (1UL<<30)
|
||||
#define CPUID_EDX_PBE (1UL<<31)
|
||||
/* CPUID.07H:EBX.TSC_ADJUST*/
|
||||
#define CPUID_EBX_TSC_ADJ (1<<1)
|
||||
#define CPUID_EBX_TSC_ADJ (1UL<<1)
|
||||
/* CPUID.07H:EDX.IBRS_IBPB*/
|
||||
#define CPUID_EDX_IBRS_IBPB (1<<26)
|
||||
#define CPUID_EDX_IBRS_IBPB (1UL<<26)
|
||||
/* CPUID.07H:EDX.STIBP*/
|
||||
#define CPUID_EDX_STIBP (1<<27)
|
||||
#define CPUID_EDX_STIBP (1UL<<27)
|
||||
/* CPUID.80000001H:EDX.Page1GB*/
|
||||
#define CPUID_EDX_PAGE1GB (1<<26)
|
||||
#define CPUID_EDX_PAGE1GB (1UL<<26)
|
||||
/* CPUID.07H:EBX.INVPCID*/
|
||||
#define CPUID_EBX_INVPCID (1<<10)
|
||||
#define CPUID_EBX_INVPCID (1UL<<10)
|
||||
/* CPUID.01H:ECX.PCID*/
|
||||
#define CPUID_ECX_PCID (1<<17)
|
||||
#define CPUID_ECX_PCID (1UL<<17)
|
||||
|
||||
/* CPUID source operands */
|
||||
#define CPUID_VENDORSTRING 0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user