Commit Graph

62 Commits

Author SHA1 Message Date
Li Fei1
460124f984 dm: e820: refine e820 layout
We don't reserve PCI MMIO in e820 Table, it's included in DSDT ACPI Table.
About 0xA0000 - 0x100000 entry, we don't have any ACPI Table touch this region.
So we could remove it too.

After this change, we could only pass the reserved e820 table which we must
reserve to OVMF. In this case, the OVMF could trust ACRN-DM and pass the
reserved e820 table to guest instead of dropping it.

This patch needs the corresponding modify in OVMF. Otherwise, the guest could
not boot.

Tracked-On: #4550
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2020-10-30 15:45:31 +08:00
Sun Peng
62c9745765 dm: pci_core: Convert print output to acrn-dm logger
Unifies the logs to pr_* interfaces instead of printf for better log management.

Tracked-On: #5267
Signed-off-by: Sun Peng <peng.p.sun@intel.com>
Reviewed-by: Chi Mingqiang <mingqiang.chi@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2020-09-10 09:33:25 +08:00
Yonghua Huang
07ed6841f5 dm:Remove deprecated terms
- remove usages of maste/slave:

Tracked-On: #5249
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2020-09-01 09:30:08 +08:00
Li Fei1
be1e3acb01 dm: remove vdev_update_bar_map callback for PCIe device
Since this callback is only useful for pass through PCIe device and now pass through
PCIe device emulation has splited from DM to HV. we could remove this callback now.

Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
2020-03-02 16:42:17 +08:00
Li Fei1
9fa6eff3c5 dm: vPCI: remove passthrough PCI device unused code
Now we split passthrough PCI device from DM to HV, we could remove all the passthrough
PCI device unused code.

Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-02-24 16:17:38 +08:00
Li Fei1
dafa3da693 vPCI: split passthrough PCI device from DM to HV
In this case, we could handle all the passthrough PCI devices in ACRN hypervisor.
But we still need DM to initialize BAR resources and Intx for passthrough PCI
device for post-launched VM since these informations should been filled into
ACPI tables. So
1. we add a HC vm_assign_pcidev to pass the extra informations to replace the old
vm_assign_ptdev.
2. we saso remove HC vm_set_ptdev_msix_info since it could been setted by the post-launched
VM now same as SOS.
3. remove vm_map_ptdev_mmio call for PTDev in DM since ACRN hypervisor will handle these
BAR access.
4. the most important thing is to trap PCI configure space access for PTDev in HV for
post-launched VM and bypass the virtual PCI device configure space access to DM.

This patch doesn't do the clean work. Will do it in the next patch.

Tracked-On: #4371
Signed-off-by: Li Fei1 <fei1.li@intel.com>
2020-02-24 16:17:38 +08:00
Junming Liu
ceb197c993 dm:keep pci bar property unchanged when updating pci bar address
When update pci bar addr,
DM may change the bar property by func pci_cfgrw.
PCI spec chapter 'Base Addresses' shows
bits 0~3 are readonly of memeory space BAR,
so this change won't happen.

This patch ensures pci bar property unchanged
when update pci bar addr.

Tracked-On: #4282

Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2020-01-13 16:47:25 +08:00
Mingqiang Chi
5267a9775c dm:replace perror with pr_err
use acrn-dm logger function instread of perror,
this helps the stability testing log capture.

Tracked-On: #4098
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2020-01-08 13:37:57 +08:00
Junming Liu
f2bf3d3ed1 dm:gvt:update bus0 memlimit32 value
Now the GVT already tries to reserve the region.
the problem is that the region should be
reflected in PCI BUS0 memlimit32 and updated to DSDT table.

As the GVT PCI bar0/2 is in reserved region
and not updated to memlimit32 in DSDT table,
the problem is triggered.

Tracked-On: projectacrn#4227

Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
2019-12-12 09:04:30 +08:00
Junming Liu
2f642002fc dm:gvt:enable gvt bar registration
Need to enable gvt bar registration, so remove the previous workaround patch.

Tracked-On: projectacrn#4005

Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2019-12-05 11:20:11 +08:00
Junming Liu
89908bf510 dm:gvt:update gvt bars before other pci devices write bar address
The current design has the following problem:
uos kernel may update gvt bars' regions,
but ACRN-DM doesn't know this update.
ACRN-DM only know out-of-date gvt bar regions,
For simplicity, mark these bar regions as OOD bar regions.
uos kernel may allocate OOD bar regions for
other pci devices, which will result in ACRN-DM
bar regions inconsistency with uos kernel.

The new design is the following:
When other pci device update bar regions
(1) ACRN-DM updates gvt bars' regions
provided by a system file.
(2) ACRN-DM updates this pci device bar regions

v5 -> v6:
	* add more comments

v4 -> v5:
	* remove & for callback func assignment

v3 -> v4:
	* compare gpu bar address to avoid unnecessary
	* unregistered/registered operation

v2 -> v3:
	* call unregister_bar and register_bar when update gvt bars
	* update gvt reserved regions when update gvt bars

Tracked-On: projectacrn#4005

Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2019-12-05 11:20:11 +08:00
Junming Liu
f27d47542a dm:gvt:adjust pci bar region with reserved bar regions
ACRN-DM has reserved gvt bar regions.

This patch ensures other pci devices' bar regions
won't overlap with reserved bar regions.

v6 -> v7:
	* rename some struct and func

v5 -> v6:
	* remove outdated comment
	* add comments for code reading
	* code cleaning about gvt bar0 and bar2 size

v4 -> v5:
	* rename adjust_bar_region and adjust_bar_region_by_gvt_bars
	* change adjust_bar_region_by_gvt_bars interface for code cleaning

v3 -> v4:
	* add static struct gvt_region  instead of definition or pointer array.

v2 -> v3:
	* repalce pci_emul_alloc_bar with gvt_reserve_resource when allocate gvt bars
	* use register_bar to detect if gvt bars confilts with pci devices

v1 -> v2:
	* don't limit the gvt bar type is MEM32 when deal with pci bar
	* add is_two_region_overlap func to detect if two regions overlap
	* add region array to store gvt bar0 and bar2 regions

Tracked-On: projectacrn#4005

Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2019-12-05 11:20:11 +08:00
Junming Liu
1ac0b57c6a dm:gvt:reserve gvt bar regions in ACRN-DM
The current design has the following problem:
gvt uses some pci bar regions,
but ACRN-DM isn't aware of these regions.
So ACRN-DM may allocate these regions for other pci devices,
which will result in other pci devices bar regions
overlap with gvt bar regions.

The new design is the following:
(1) ACRN-DM reads gvt bar regions
which are provided by physical gpu;
(2) ACRN-DM reserves gvt bar regions

v6 -> v7:
	* use array to store reserved bar regions
	* rename some struct and func

v5 -> v6:
	* rename enable_gvt to gvt_enabled
	* add a interface to reserve bar regions
	* reserve gvt bar regions

Tracked-On: projectacrn#4005

Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Liu XinYun <xinyun.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2019-12-05 11:20:11 +08:00
Mingqiang Chi
a59205f6a2 dm:use acrn-dm logger function instread of fprintf
use acrn-dm logger function instread of fprintf,
this helps the stability testing log capture.

Tracked-On: #4098
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Cao Minggui <minggui.cao@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2019-11-14 15:34:04 +08:00
Mingqiang Chi
5375a1613b dm:use acrn-dm logger function instread of printf
Use acrn-dm logger function instread of printf,
this helps the stability testing log capture.

Tracked-On: #4098
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Cao Minggui <minggui.cao@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2019-11-14 15:34:04 +08:00
Gao Junhao
90cf27aa5f dm: remove cfc/cf8 pio handler
The acrn vhm driver will convert all PCI configure space access to
PCI_CFG type, so the pci_emul_cfgaddr and pci_emul_cfgdata will nerver
be invoked. Remove these useless functions.

Tracked-On: #3999
Signed-off-by: Gao Junhao <junhao.gao@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2019-11-05 16:07:38 +08:00
Gao Junhao
43b2327eb8 dm: validation for input to public functions
slot value should be checked in range before used to access
bi->slotinfo[].

Tracked-On: #3822
Signed-off-by: Gao Junhao <junhao.gao@intel.com>
Reviewed-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2019-10-16 10:26:50 +08:00
Yonghua Huang
842da0ac1e dm: cleanup assert in core.c
- check input by condition check, instead of assert.
 - remove redundant header file including for some files.

Tracked-On: #3252
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Shuo Liu <shuo.a.liu@intel.com>
2019-07-05 09:36:02 +08:00
Shuo A Liu
2b3dedfb9b dm: pci: clean up assert() in pci core
Tracked-On: #3252
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Yonghua Huang <yonghua.huang@intel.com>
2019-06-20 11:21:51 +08:00
Yan, Like
771f15cd6b dm: don't present ioapic and pic to RT VM
Per ACRN RT VM design, there is no virtual IOAPIC and virtual PIC emulated for RT VM.
This commit removes the entries of IOAPIC, PIC, PPRT and APRT in ACPI table for RT VM.

Tracked-On: #3227
Signed-off-by: Yan, Like <like.yan@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2019-06-12 14:29:50 +08:00
Jian Jun Chen
b98096ea06 dm: pci: fix the MMIO regions overlap when getting bar size
PCI spec says that the procedure of sizing a BAR is as follows:
1) disable the decode via command register
2) save the original value of BAR register
3) write all-1 to the BAR register
4) read BAR register back, calculate the size
5) restore the original value to BAR register
6) re-enable the decode via command register

Some driver does not disable the decode of BAR register via the
command register before sizing a BAR. This will lead to a overlay
of the BAR addresses when trying to register the intermediate
BAR address via register_bar. A stateful variable sizing is used
to keep track of such kind of BAR address changes and workaroud
this violation.

Currently this issue is only found when audio device is passed
through to Windows 10 guest. When it is fixed in the Windows
audio driver, this patch should be reverted.

v1 -> v2:
- change the commit message to add the procedure of BAR sizing from
  PCI spec

Tracked-On: #2962
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2019-06-03 09:14:15 +08:00
Jian Jun Chen
811d1fe93d dm: pci: update MMIO EPT mapping when update BAR address
For PCI passthrough device when guest OS updates the BAR address
the corresponding EPT mapping should be updated as well.

Tracked-On: #2962
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Signed-off-by: Liu Shuo A <shuo.a.liu@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
2019-05-30 14:19:14 +08:00
Liu Xinyun
d9e6cdb593 dm: not register/unregister gvt bar memory
AcrnGT traps and intercepts the memory region defined by PCI bar in
service OS kernel driver. No need to register the bar associated region
in dm. By the way, some OS changes BAR start address and there is no
mechanism to reflect the gvt changes back to dm. It causes problem that
other devices may register new region which falls in GVT `old` region,
and leads to hypervisor crash.

v4: Add FIXME tag. It's a short term solution before migrated to OVMF
v3: rewording the comments
v2: removed unnecessary braces and use printf to log (Peter)

Tracked-On: #2976

Reviewed-by: He, Min <min.he@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Signed-off-by: Liu Xinyun <xinyun.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2019-05-09 17:28:16 +08:00
Vijay Dhanraj
71b56e0eed DM: Virtio-Blk Rescan
This patch adds support to trigger rescan of virtio-blk device by the
guest VM. This is an alternate to hot-plugging virtio-blk device.
This feature stems from the kata requirement, which hot-plugs container
rootfs after the VM is launched.

As part of virtio-blk rescan,
1. Update the backing file for the virtio-blk device with valid file.
   Basically update the empty file (with dummy bctxt) that was passed
   during VM launch.
2. Update virtio-blk device configurations for udpated backing file.
3. Update size associated with valid backing file in the config space.
4. Notify guest OS, of the new config change.
5. On this notification, guest will do the following.
	(i). Update virtio-blk capacity.
 	(ii). Revalidate the disk.
 	(iii). Identify the newly plugged block device.

v5 -> v6:
- Removed use of dummy file and added a new parameter "nodisk"
  to virtio-blk which indicates user wants to create a virtio-blk
  device with dummy backend.
- Moved vm_monitor_rescan from pci core to virtio-blk as it currently
  applies to only virtio-blk.

v4 -> v5:
- Reverted back logic, so that blkrescan is only supported when
  VM is launched with empty backend file.

v3 -> v4:
- Close block context before allocating a new one
- Allow backend filepath  with additional options to be more generic
- Remove blank lines introduced as part of previous patches.

v2 -> v3:
- Renamed vdev ops vdev_blk rescan to vdev_rescan
- Renamed montior ops virtio_blkrescan_ops to virtio_rescan_ops
- Consolidated virtio-blk configuration specific part into
  a separate function
- Removed size requirement in acrnctl command.

v1 -> v2:
- Added more comments in the code.
- Renamed APIs from displug to blkrescan, inline with acrnctl cmd.
- Split the patch into two. This corresponds to changes in acrn-dm.

Tracked-On: #3051
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2019-05-07 09:08:50 +08:00
Minggui Cao
c3d60297f2 DM: use log macro/func to output log info
also add logs for some key entries.

Tracked-On: #3012
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
2019-05-05 19:13:07 +08:00
Peter Fang
a718fbe860 dm: pci: change return type to bool
Change return type to bool when returning int is not necessary.

Tracked-On: #2902
Signed-off-by: Peter Fang <peter.fang@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
2019-04-22 15:18:21 +08:00
Jian Jun Chen
8115857956 dm: pci: unregister bars which are still enabled in pci_emul_free_bars
Guest OS for example Windows will disable bars before shutdown. Bars
are unregistered when they are disabled. Trying to unregister a bar
which has been unregistered causes a assertion. In pci_emul_free_bars
only those enabled bars should be unregistered.

Tracked-On: #2962
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
2019-04-16 15:03:04 +08:00
Liu Shuo A
d648df766c dm: register_bar/unregister_bar when bar enable/disable
Sometimes guest OS writes PCIR_COMMAND register to disable the device,
then update the bar address followed by a write to PCIR_COMMAND register
to enable the device again. In this case unregister_bar/register_bar
should be called otherwise the IO/MMIO regions monitored by device model
will not be updated accordingly.

Tracked-On: #2962
Signed-off-by: Yu Wang <yu1.wang@intel.com>
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Signed-off-by: Liu Shuo A <shuo.a.liu@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
2019-04-16 15:03:04 +08:00
Peter Fang
20164799cb dm: leave a gap for 32-bit PCI hole in E820 map
Guest OS (e.g. Linux) may rely on a gap in E820 map in the 32-bit memory
space to determine the MMIO space for its PCI devices. Leave this gap
when building E820 map to keep the guest's PCI subsystem working.

After commit 7752d5cfe3d11ca0bb9c673ec38bd78ba6578f8e, Linux kernel no
longer requires the MMCONFIG region to be reserved in the E820 map.
Nonetheless, keep it in the reserved region to be on the safe side.

Tracked-On: #2843
Signed-off-by: Peter Fang <peter.fang@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
2019-03-25 13:49:48 +08:00
Peter Fang
263b486a09 dm: pci: add MMIO fallback handler for 64-bit PCI hole
Add the PCI MMIO fallback handler to the 64-bit PCI host aperture, so
that the guest won't inadvertently crash acrn-dm due to unhandled MMIO.

Tracked-On: #2792
Signed-off-by: Peter Fang <peter.fang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
2019-03-21 10:28:17 +08:00
Minggui Cao
5397200118 DM: fix memory leak
1. free memory allocated by strdup in blockif_open
2. free msix.table when its pci device deinit

Tracked-On: #2704
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
2019-03-14 15:17:30 +08:00
Binbin Wu
f572d1ecdd [RevertMe] dm: pci: restore workaround when alloc pci mem64 bar
There was a workaround in DM that allocates PCI 64bit mem bar in 32bit mem space
if the bar size is within 32MB.

After the workaround being removed, there is an issue to enter fastboot
mode for inappropriate handling of 64bit mem bar in guest driver.
The patch bring the workaround back, and skip the workaround when the guest
is booted by OVMF.

Revert the patch after the guest fixs the issue of handling 64bit mem bar in
fastboot mode.

Tracked-On: #2677
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2019-03-05 15:14:24 +08:00
Jian Jun Chen
29b1ebcd43 dm: add support of high MMIO mapping
1G PCI hole is added just after 4G address which is used as the
PCI high MMIO address space. Guest high memory is mapped from 5G
address for both EPT and device model user space address. Guest
e820 table and API vm_map_gpa are updated accordingly.

Tracked-On: #2577
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2019-02-28 18:33:11 +08:00
Liu Shuo A
32925c10bd dm: allocate 64bit MMIO above 4G strictly to pass OVMF check
Remove the >32MB limitation for 64bits mmio hole allocation, ACRN
hasn't met such buggy devices for this limitation. Besides, OVMF
has one bug which requires 64bits BAR must allocate from 4G+ address,
otherwise trigger assert. This patch can workaround it.

Tracked-On: #2577
Signed-off-by: Liu Shuo A <shuo.a.liu@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2019-02-28 18:33:11 +08:00
Shuo Liu
aed75145c1 dm: Limit 64 bits PCI BAR region address space
Limit 64 bits PCI BAR space from 0x100000000UL ~ 0x140000000UL,
as HV now only support 0x400000000UL+0x80000000 as top of guest memory
address. EPT table size is static allocated.

Tracked-On: #2577
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2019-02-28 18:33:11 +08:00
Shuo A Liu
3e0b06cfd6 dm: Fix some issues from string operations
The patch fix some string operations issues and also improve readability
of several snippet.

Tracked-On: #2133
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Yonghua Huang <yonghua.huang@intel.com>
2018-12-25 18:40:04 +08:00
Long Liu
5ab68eb97b dm: hw: Replace sscanf with permitted string API
Replace sscanf in device model hw directory

Tracked-On: #2079
Signed-off-by: Long Liu <long.liu@intel.com>
Reviewed-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: <yonghua.huang@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2018-12-17 19:17:29 +08:00
Peter Fang
e835f5f5d2 dm: enforce data size when accessing PCI BARs
Always enforce data size when using BAR access functions.

Currently, the size serves as a hint to the BAR access functions and
these functions are expected to behave accordingly. Some of the access
functions, e.g. virtio ones, don't always truncate the data but expect
the caller to take care of the data size. This causes problems with
OVMF's virtio drivers during I/O instruction emulation because RAX can
contain junk bits that shouldn't be written to the device.

v1 -> v2:
- improve readability

Tracked-On: #1935
Signed-off-by: Peter Fang <peter.fang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-12-13 13:22:44 +08:00
Junjie Mao
97eb72a4a0 doc: always use 'None' for functions not returning a value
It is preferred to state the absence of a return value explicitly in the
doxygen-stile comments. Currently there are different styles of doing this,
including:

  @return None
  @return NULL
  @return void
  @return N/A

This patch unifies the above with `@return None`.

Tracked-On: #1595
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
2018-11-30 14:55:17 +08:00
Shuo Liu
d261b4bce2 doc: update virtio related functions doc comments
Update some virtio, VBS-K, vhost APIs documents.

Tracked-On: #1595
Signed-off-by: Shuo Liu <shuo.a.liu@intel.com>
2018-11-04 20:32:50 -08:00
Yin Fengwei
8787b65fde dm: fix the issue when guest tries to disable memory range access
According to PCI spec 3.0 section 6.2.2 "Device Control", guest
could write the command register to control device response to
io/mem access.

The origial code register/unregister the memory range which is
not suitable because it can't handle the sequence:
  1. disble the device response to specific memory range
  2. reboot guest (DM will try to free the memory range which
     was freed in step 1 already)

Tracked-On: #1277
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2018-10-08 12:57:00 +08:00
Yin Fengwei
be0cde7dec Revert "dm: workaroud for DM crash when doing fastboot reboot"
Remove the workaround and will submit the fixing patch.

Tracked-On: #1277
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2018-10-08 12:57:00 +08:00
Yin Fengwei
4a038d18b1 dm: workaroud for DM crash when doing fastboot reboot
This is temperory workaround for DM crash when doing fastboot
reboot. In fastboot, it will disable USB host functionality by
disable device respsone to one PCI bar. While DM code just release
the bar in this case. Which break the reboot functionality.

The workaround is to remove the assert to avoid DM abort. This is
safe because reboot will remove all memory range registered.

We will have offiical fixing later.

Tracked-On: #1277
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2018-09-19 10:47:59 +08:00
Li Zhijian
bcfe447f5c DM: deinit initialized pci device when failed
if some pci devices behind gvt got failures when initlizing at init_pci(), gvt
instance have no chance to be destroied even acrn-dm exits.

NOTE: this patch can not work standalone, a following patch to kernel
side(643d40961cf: "vhm: init client->kthread_exit true") is requied as well,
otherwise it will stucks during destroying gvt instance.

Tracked-On: #1141
Signed-off-by: Li Zhijian <zhijianli88@163.com>
2018-09-10 10:14:01 +08:00
Yin Fengwei
9878543356 DM: add system reset (with RAM content kept)
This function add high level reset_vdev function. Which is
implemented to call deinit/init pairing to emulate the virtual
device reset operation.

This patch also add the system reset which keep the UOS RAM
content functionality to DM.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-07-17 14:11:12 +08:00
Shiqing Gao
789899d05f dm: deal with physical GSI sharing
- hardcode the devices' GSI info based on the platform
- reject the passthrough if the following requirement is not met
  all the PCI devices that are sharing the same GSI should be assigned
  to same VM to avoid physical GSI sharing between multiple VMs.

v4 -> v5
 * Move the gsi_dev_mapping_tables definition in a separate file
 * Add the GSI info that might be used by GPIO
 * Update the HW name

v3 - > v4
 * Refine the format of raw data to improve the readability
 * Remove the redundant code when adding the new dev into the gsi
    sharing group

v2 -> v3
 * Add the MSI/MSI-x capability check
   Do not add the device which supports MSI/MSI-x to the GSI sharing
   group.

v1 -> v2
 * Update the GSI raw data based on SBL
 * Free the resources when gsi sharing violation occurs
 * Move the MACRO PCI_BDF(b, d, f) to pci_core.h since passthrough.c
    and gsi_sharing.c are both using it

Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Edwin Zhai <edwin.zhai@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-29 00:50:01 +08:00
Anitha Chrisanthus
9d4cc5c11d dm: Change the PCI_EMUL_MEMBASE64 to workable address.
To enable GPU passthru, BAR2 allocation had problems when the allocation
is above the 4GB memory.This change is to accomodate the 256MB aperture
allocation in BAR2 to a more managable address.

v2: changed the MEMBASE64 address instead of increasing the mem_size.

Signed-off-by: Anitha Chrisanthus <anitha.chrisanthus@intel.com>
Reviewed-by: Gong Zhipeng <zhipeng.gong@intel.com>
2018-06-29 00:50:01 +08:00
Xinyun Liu
fb723efa48 dm: check pci_vdev before using
acrn-dm runs to segmentation fault when failed to create VMs with
improper parameters.

If vdevs failed to be created, they are still be freed in deinit(),
and dereference the null pointers leads to segfault.

Signed-off-by: Xinyun Liu <xinyun.liu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-06-20 11:29:21 +08:00
Zide Chen
df4ab92e81 DM: cleanup for header inclusions
used https://gitlab.com/esr/deheader to detect and remove unnecessary
header file inclusions

Signed-off-by: Zide Chen <zide.chen@intel.com>
2018-06-07 14:35:30 +08:00
Jian Jun Chen
b25a30f271 dm: add default handling in pci_emul_capwrite
Virtio 1.0 introduced several PCIY_VENDOR capabilities. When trying to
write to these capabilities no action is taken so the registers in
the capability of VIRTIO_PCI_CAP_PCI_CFG such as bar, offset and length
remain the default value 0. Later a read or write of pci_cfg_data needs
these information to perform the indirect read or write to the bar
region.

Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Hao Li <hao.l.li@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-31 11:25:15 +08:00