Move the function which are used to get available ttysn
from board catalogue to library catalogue
Tracked-On: #5154
Signed-off-by: Shixiong Zhang <shixiongx.zhang@intel.com>
Comments will be added for the HV_SUPPORTED_MAX_CLOS/MAX_MBA_CLOS_NUM_ENTRIES/MAX_CACHE_CLOS_NUM_ENTRIES
macros in generated code
Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Move struct pt_intx_config vm0_pt_intx[] defintion to pt_intx.c
so that vm_configurations.h/vm_configurations.c are consistent for different boards
Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
so that vm_configurations.h/vm_configurations.c are consistent for different boards
The boilerplate code is protected by #ifdef VM0_PASSTHROUGH_TPM/#endif, so it will
not hurt if we always produce related code.
Define a new macro VM0_TPM_BUFFER_BASE_ADDR_GPA to define the allocated gpa for VM0_TPM_BUFFER_BASE_ADDR
to make the code more flexible.
Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
so that vm_configurations.h/vm_configurations.c are consistent for different boards
Debugged and refactored the split_cmdline() function
Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
so that vm_configurations.h/vm_configurations.c are consistent for different boards
Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
so that vm_configurations.h/vm_configurations.c are consistent for different boards
Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
1.Add macro MAX_CACHE_CLOS_NUM_ENTRIES for CAT, and MAX_MBA_CLOS_NUM_ENTRIES for MBA.
MAX_MBA_CLOS_NUM_ENTRIES:
Max number of Cache Mask entries corresponding to each CLOS.
This can vary if CDP is enabled vs disabled, as each CLOS entry will have corresponding
cache mask values for Data and Code when CDP is enabled.
MAX_CACHE_CLOS_NUM_ENTRIES:
Max number of MBA delay entries corresponding to each CLOS.
2.Move VMx_VCPU_CLOS macro to misc_cfg.h head file.
Tracked-On: #5229
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
We use sos kernel cmdline maxcpus to limit the pCPU number of SOS
for hybrid or hybrid_rt scenarios by vcpu numbers calculation.
v2: add SOS CPU affinity calculation by total pCPU plus pCPUs
occupied by pre-launched VMs when no pcpuid configured
in SOS.
Tracked-On: #5216
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
Fix build issue while CDP_ENABLED=y for EHL-CRB-B.
Tracked-On: #5092
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Add support to generate passthru TPM information for whl-ipc-i5/i7.
Tracked-On: #5077
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
There is some macro defined in misc_cfg.h while CAT/MBA enabled.
include the missing header to solve build issue.
Tracked-On: #5092
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Now the hypervisor configuration source code layout is changed, so acrn-config
need to change accordingly to make sure XML based configuration build success;
Tracked-On: #5077
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Refine sanity check for RDT CLOS and MBA Delay.
Tracked-On: #4943
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Reviewed-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
generate msix emulation information from known exist PCI devices for
board config.
Tracked-On: #4831
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Currently, MMIO PCI BDF of ttyS was indexed by IRQ, but it may found
the wrong BDF when the IRQ was shared and it is not expected. So, the
patch uses the MMIO base to query /proc/iomem to find BDF, the waring
will get if BDF is not present in iomem.
Tracked-On: #4862
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
As VUART is not supported PCI VUART, use native PCI ttySn's IRQ for
VUART1 would cause communication failed, allocate a free IRQ for it.
Tracked-On: #4798
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Add max VM count check when generating scenario XML file.
Tracked-On: #4641
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
For purpose weaken 'scenario' from config tool, remove 'scenario' dependency
from config tool.
Tracked-On: #4641
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
Rounding HI_MMIO_START, HI_MMIO_END to the closest 1G. This avoids
round up logic in the hypervisor.
Tracked-On: #4586
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Board config should relay on library/common.py and board_cfg_lib, then
remove the duplicate parameters and functions.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
Find the 64-bit mmio window from /proc/iomem to generate HI_MMIO_START/HI_MMIO_END.
Tracked-On: #4569
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
value among RDT resources.
This patch identifies the least common supported clos value
from multiple RDT resource. This is done so as to have
consistent capabilities across all resource allocations.
From SDM, "The number of CLOS supported for the MBA feature
may or may not align with other resources such as L3 CAT. In
cases where the RDT features support different numbers of
CLOS the lowest numerical CLOS support the common set of
features, while higher CLOS may support a subset. For instance,
if L3 CAT supports 8 CLOS while MBA supports 4 CLOS, all 8 CLOS
would have L3 CAT masks available for cache control, but the
upper 4 CLOS would not offer MBA support. In this case the upper
4 CLOS would not be subject to any throttling control. Software
can manage supported resources / CLOS in order to either have
1) consistent capabilities across CLOS by using the common subset
or 2) enable more flexibility by selectively applying resource
control where needed based on careful CLOS and thread mapping".
We decided to go with option #1, as it will be more consistent
and less prone to user errorw hen programming the resource mask
MSRs.
Tracked-On: #3715
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Currently, config tool will maintain a whitelist for the board which
need to hide some pci devices. For the board out of whitelist, we set
MAX_HIDE_PDEVS_NUM to 0.
Tracked-On: #3475
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
The macro definition is changed in hypervisor code, so modify acrn-config
side accordingly.
Tracked-On: #4230
Signed-off-by: Victor Sun <victor.sun@intel.com>
SOS vm only support legacy serial port emulation, so we need to
hide non-legacy serial ports from webUI when user want to select
serial port as SOS console.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1. unify get_vuart_info_id/get_vuart_id api in board/scenario/launch
config tool.
2. if vm use 'vuart1(tty)' method to power off, make sure this vm have
select the vuart1 'SOS_COM2_BASE'.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
There may be no physical serial port in the target board, and it will
stop generating board file, the patch add support to handle such case.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Since msr_index relys on the MSR_IA32_L2_QOS_MASKn(n:max to 3)
macro which defined in hv source code, generate array that CLOS number
more than 4 means need define more than 4 macro.
This patch solve such issue by using MSR_IA32_L2/L3_MASK_BASE with the
msr index offset.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
The value of CONFIG_MAX_PCPU_NUM is stands for Processor CPU number and
it is grabed from board information.
Tracked-On: #3798
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1.the script will parse the the board information which already
generated, $(scenario).xml modified by user, generate scenario
vm configuration and apply to the acrn-hypervisor source code base.
2.parse cpu/memory/ttys/rootfs information from native os and store it to
the source code
3.implemnt scenario_config and it's usage
usage: scenario_cfg_gen.py --board <board_info_file> -scenario <scenario_info_file>
board_info_file : file name of the board info
scenario_info_file : file name of the scenario info
sample:
$ python3 scenario_cfg_gen.py --board ../board-xmls/apl-mrb.xml
--scenario ../config-xmls/scenarios/sdc.xml
Also improvement board config generate usage:
sample:
$ python3 board_cfg_gen.py --board ../board-xmls/apl-mrb.xml
--scenario ../config-xmls/scenarios/sdc.xml
V1-V2:
1). parse board_setting.xml was removed as these configuration will be
stitch into scenario configuration
2). parse console for different formats
3). parse epc sections
4). add logical partition rootfs
5). support to parse clos, while webui set to None type
6). support to parse bootargs, while webui set to nul
7). convert '-' to '_' for pci sub class name while generating source file
Tracked-On: #3602
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
