Two PSE-GPIO controllers of EHL CRB require MSI-X emulation for
pass-thru because it uses multiple MSI vectors. Currently acrn-config
enables MSI-X emulation for only TSN devices. Enable MSI-X emulation
for PSE-GPIOs, too.
Tracked-On: #5242
Signed-off-by: Toshiki Nishioka <toshiki.nishioka@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1.Add macro MAX_CACHE_CLOS_NUM_ENTRIES for CAT, and MAX_MBA_CLOS_NUM_ENTRIES for MBA.
MAX_MBA_CLOS_NUM_ENTRIES:
Max number of Cache Mask entries corresponding to each CLOS.
This can vary if CDP is enabled vs disabled, as each CLOS entry will have corresponding
cache mask values for Data and Code when CDP is enabled.
MAX_CACHE_CLOS_NUM_ENTRIES:
Max number of MBA delay entries corresponding to each CLOS.
2.Move VMx_VCPU_CLOS macro to misc_cfg.h head file.
Tracked-On: #5229
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
HV_SUPPORTED_MAX_CLOS:
This value represents the maximum CLOS that is allowed by ACRN hypervisor.
This value is set to be least common Max CLOS (CPUID.(EAX=0x10,ECX=ResID):EDX[15:0])
among all supported RDT resources in the platform. In other words, it is
min(maximum CLOS of L2, L3 and MBA). This is done in order to have consistent
CLOS allocations between all the RDT resources.
Tracked-On: #5229
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Fix build issue while CDP_ENABLED=y for EHL-CRB-B.
Tracked-On: #5092
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
There is some macro defined in misc_cfg.h while CAT/MBA enabled.
include the missing header to solve build issue.
Tracked-On: #5092
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Now the hypervisor configuration source code layout is changed, so acrn-config
need to change accordingly to make sure XML based configuration build success;
Tracked-On: #5077
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Refine sanity check for RDT CLOS and MBA Delay.
Tracked-On: #4943
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Reviewed-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
This patch adds support to configure MBA delay values from
scenario xml files just as it is done for CAT mask. This will
improve user experience when configuring RDT resource mask
values.
Tracked-On: #4943
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
generate msix emulation information from known exist PCI devices for
board config.
Tracked-On: #4831
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1.Add parser and sanity check for RDT_ENABLED/CDP_ENABLED/CLOS_MASK.
2.Skip to generate RDT inforamtion when HW not support RDT or usr
select 'n' to disable RDT feature.
3.Add contiguous bit 1 check for CLOS_MASK.
Tracked-On: #4860
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This patch sets defaults similar to generic platform configuration
when leaf features like PM_INFO, S3_INFO, S5_INFO, DRHD_INFO, CPU_BRAND,
CX_INFO, PX_INFO, MMCFG_BASE_INFO are not generated via either target
offline tool or user supplies empty field in case of emulation.
Tracked-On: #3198
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Board config should relay on library/common.py and board_cfg_lib, then
remove the duplicate parameters and functions.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
This patch adds support for,
1. Storing MBA resource and its max supported clos value
in the target xml file under clos subsection.
2. Generating board.c file with MBA RDT resource.
Tracked-On: #3725
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
This patch adds support for as generating board.c file
with multiple RDT resources.
Tracked-On: #3715
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Currently, config tool will maintain a whitelist for the board which
need to hide some pci devices. For the board out of whitelist, we set
MAX_HIDE_PDEVS_NUM to 0.
Tracked-On: #3475
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Set the DRHDx_IGNORE to false even there is no DEV_SCOPE under this
DRHD.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Skip to generate DRHDn_IGNORE to board.c, when there is no device scope
type on target platform DRHD definition.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Current board parse logic would be broken if acpi_idle/acpi-cpufreq
driver is not loaded by native kernel.
This patch would just leave a warning to user and continue to parse
other information in this case.
Tracked-On: #4082
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
without the msr.h file the build will be failed when CAT is enabled.
Tracked-On: #4066
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1. Parse DRHD_INFO section from board config xml, and generate dmar
structure information to board.c
2. Copy macro of DRHD_INFO from board config xml to $(board)_acpi_platform.h
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
Since msr_index relys on the MSR_IA32_L2_QOS_MASKn(n:max to 3)
macro which defined in hv source code, generate array that CLOS number
more than 4 means need define more than 4 macro.
This patch solve such issue by using MSR_IA32_L2/L3_MASK_BASE with the
msr index offset.
Tracked-On: #3854
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
1.the script will parse the the board information which already
generated, $(scenario).xml modified by user, generate scenario
vm configuration and apply to the acrn-hypervisor source code base.
2.parse cpu/memory/ttys/rootfs information from native os and store it to
the source code
3.implemnt scenario_config and it's usage
usage: scenario_cfg_gen.py --board <board_info_file> -scenario <scenario_info_file>
board_info_file : file name of the board info
scenario_info_file : file name of the scenario info
sample:
$ python3 scenario_cfg_gen.py --board ../board-xmls/apl-mrb.xml
--scenario ../config-xmls/scenarios/sdc.xml
Also improvement board config generate usage:
sample:
$ python3 board_cfg_gen.py --board ../board-xmls/apl-mrb.xml
--scenario ../config-xmls/scenarios/sdc.xml
V1-V2:
1). parse board_setting.xml was removed as these configuration will be
stitch into scenario configuration
2). parse console for different formats
3). parse epc sections
4). add logical partition rootfs
5). support to parse clos, while webui set to None type
6). support to parse bootargs, while webui set to nul
7). convert '-' to '_' for pci sub class name while generating source file
Tracked-On: #3602
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
1. add misc.py to get systemd ram and root device
2. add more specify comments for arguments of functions
v1-v2:
typo: Parser -> Parse
some grammar check
v2-v3:
add the message for Cx state
Tracked-On: #3602
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Terry Zou <terry.zou@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
the script will parser the the board information which already generated on
target board, and apply to the acrn-hypervisor as a patch.
usage: board_cfg_gen.py --board <board_info_file>
sample:
$ python3 board_cfg_gen.py --board ../target_board/board_info.xml
v1-v2:
1. allow to generate new board patch
v2-v3:
1. modify the description of generator tools
2. parser board_name.xml file
3. coding as PEP8 guildline
Tracked-On: #3480
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Reviewed-by: Shuang Zheng shuang.zheng@intel.com
Acked-by: Terry Zou <terry.zou@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
