Commit Graph

7 Commits

Author SHA1 Message Date
Zheng, Gen
b6dd16b75e MMU: bug fix on operating va <=> pa convertion
Before referencing to physical address of devs such as lapic, ioapic,
vtd, and uart, switch to virtual address.
Use a phisical address of pml4 to write CR3.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-04-17 11:33:30 +08:00
Zheng, Gen
bde415ec81 refine: change the address arguments type of mmio access api
Change the address arguments type of mmio access api from uint64_t
to void*.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-04-17 11:33:30 +08:00
Zheng, Gen
c92da5295b refine: remove redundant data type definition
remove data defination of mmio_addr_t, vaddr_t, paddr_t,
and ioport_t.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-04-13 23:51:40 +08:00
Li, Fei1
f6457e9cc1 hv: lapic: export write_lapic_reg32
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-03-28 10:46:32 +08:00
Li, Fei1
bf1a312fa6 Add cpuinfo_x86 to cache cpu capability/feature
Add a global boot_cpu_data to cache common cpu capbility/feature
for detect cpu capbility/feature.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Xu, Anthony <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-03-23 08:03:11 +00:00
Jason Chen CJ
d1237e81f0 uefi: init vlapic according to native lapic
this patch save native lapic configuration and restore it to vm0's vlapic
before its running, then doing hpet timer interrupt injection through vlapic
interface -- this will not mess up vlapic and we can see hpet
timer interrupt coming continuously.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-03-21 12:14:01 +08:00
Eddie Dong
f4cd4338fd initial import
internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085

Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-03-07 21:05:38 +08:00