Commit Graph

5 Commits

Author SHA1 Message Date
Zide Chen
8c398f7d7e hv: fix issues when msi-x shares same BAR with other data structures
If PBA or other data structures reside in the same BAR with MSI-X,
devicemodel could emulate them and make hypercall SET_MEMORY_REGION
to setup EPT for vm0.

Hypervisor can not intercept the whole range of this BAR, but only
the minimum 4KB pages that cover the MSI-X Table.

Tracked-On: #1568
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-11-01 21:22:10 +08:00
Zide Chen
5cbe079e24 hv: MSI-X Message Address write fix
Some PCI devices can not accept DWORD write to the MSI-X Table though
PCI Spec allows it:

PCI Spec 3.0 6.8.3.2 MSI-X Configuration: Specifically, software is
always permitted to fill in the Message Address and Message Upper Address
fields with a single QWORD write.

Tracked-On: #1568
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-11-01 21:22:10 +08:00
Zide Chen
dbe156e9f6 hv: fix misrac violations in vcpi code
Fixed the following violations:
- Widening cast on complex integer expression
- Casting operation to a pointer
- Static procedure is not explicitly called in code analysed

Tracked-On: #1568
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-11-01 21:22:10 +08:00
Zide Chen
5555a2f85d hv: fix bug in sizing MSI-X Table Base Address Register
To sizing a 64-bit BAR, need to form the two 32-bit registers as a
64-bit words, before doing the calculation: inverting all bits and
incrementing by 1.

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-11-01 21:22:10 +08:00
Zide Chen
7c506ebc69 hv: implement msix.c for MSI-X remapping
Similar to MSI emulation, this patch emulates the Message Control word
within MSI-X Capability Structure.

Also it emulates MSI-X table. MSI-X remapping is triggered when the guest
is changing the Mask bit in Vector Control, or the Message Data/Addr when
MSI-X Enable bit is set.

Tracked-On: #1568
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-10-29 14:29:37 +08:00