2 Commits

Author	SHA1	Message	Date
Jian Jun Chen	1949c0b52f	hv: riscv: add get/set_pcpu_id and start_pcpus implementation ... Use tp register to hold the current logical CPU ID. This follows the same design as x86 which uses MSR_IA32_SYSENTER_CS for the same purpose. riscv uses SBI HSM to start the APs. Tracked-On: #8791 Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-09-23 11:30:38 +08:00
Haicheng Li	052a58d87d	hv: multiarch: riscv: add two cpu interfaces ... add wait_sync_change and arch_get_pcpu_num implementation for riscv. MAX_PCPU_NUM comes from board_info.h generated by config tool. v2->v3: remove riscv cpu.c include asm/cpu.h v1->v2: implement arch_get_num_available_cpus(); Tracked-On: #8801 signed-off-by: Haicheng Li <haicheng.li@intel.com> Co-developed-by: hangliu1 <hang1.liu@intel.com> Signed-off-by: hangliu1 <hang1.liu@intel.com> Reviewed-by: Wang, Yu1 <yu1.wang@intel.com> Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>	2025-09-19 15:04:55 +08:00