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https://github.com/projectacrn/acrn-hypervisor.git
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1949c0b52f
Use tp register to hold the current logical CPU ID. This follows the same design as x86 which uses MSR_IA32_SYSENTER_CS for the same purpose. riscv uses SBI HSM to start the APs. Tracked-On: #8791 Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
50 lines
1.1 KiB
C
50 lines
1.1 KiB
C
/*
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* Copyright (C) 2018-2022 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*
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*/
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#include <types.h>
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#include <per_cpu.h>
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#include <cpu.h>
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#include <delay.h>
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#include <asm/sbi.h>
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#include <asm/pgtable.h>
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extern void _start_secondary_sbi(uint64_t phy_stack_addr);
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/* wait until *sync == wake_sync */
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void wait_sync_change(volatile const uint64_t *sync, uint64_t wake_sync)
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{
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while ((*sync) != wake_sync) {
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cpu_relax();
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}
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}
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uint16_t arch_get_pcpu_num(void)
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{
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return NR_CPUS;
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}
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void arch_start_pcpu(uint16_t pcpu_id)
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{
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int64_t ret;
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uint64_t pcpu_sp, phy_stack_addr;
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uint32_t hart_id = per_cpu(arch.hart_id, pcpu_id);
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uint64_t phy_start_addr = hva2hpa((void *)_start_secondary_sbi);
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pcpu_sp = (uint64_t)&per_cpu(stack, pcpu_id)[CONFIG_STACK_SIZE - 1];
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pcpu_sp &= ~(CPU_STACK_ALIGN - 1UL);
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phy_stack_addr = hva2hpa((void *)pcpu_sp);
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ret = sbi_hsm_start_hart(hart_id, phy_start_addr, phy_stack_addr);
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if (ret != SBI_SUCCESS) {
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pr_fatal("Failed to start cpu%hu by SBI HSM", pcpu_id);
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}
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}
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