HECI Bus Message is important for HECI clients communication. They use
HBM for connect, disconnect, get property and so on. In backend service,
we need do some emulation for HBM as we are running on top of native
MEI driver.
Signed-off-by: Liu Shuo <shuo.a.liu@intel.com>
Reviewed-by: Li Hao <hao.l.li@intel.com>
Reviewed-by: Wang Yu <yu1.wang@intel.com>
Reviewed-by: Zhao, Yakui <yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Backend service access the native HECI driver through MEI driver
interface in service OS. Some MEI clients need to be multiplexed,
the backend service will engage necessary service at clients filter.
TX thread is for passing data from guest to host MEI driver, then to
native hardware. RX thread is for passing data from native hardware to
guest.
Signed-off-by: Liu Shuo <shuo.a.liu@intel.com>
Reviewed-by: Li Hao <hao.l.li@intel.com>
Reviewed-by: Wang Yu <yu1.wang@intel.com>
Reviewed-by: Zhao, Yakui <yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This patch implement HECI virtualization backend service based on virtio
userspace framework. This service introduce a virtio-heci device model
for DM, and can be enabled by DM parameter '-s [BUS NO],virtio-heci'.
The HECI virtualization need both backend service in device-model and
frontend driver in guest to work. Backend service mainly emulates HECI
device's behaviors to satisfy frontend driver. They are based on virtio
userspace framework. Currently, it is using two virtqueues, one is for
TX and another is for RX.
Signed-off-by: Liu Shuo <shuo.a.liu@intel.com>
Reviewed-by: Li Hao <hao.l.li@intel.com>
Reviewed-by: Wang Yu <yu1.wang@intel.com>
Reviewed-by: Zhao, Yakui <yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
When the device has experienced an error from which it cannot
re-cover, DEVICE_NEEDS_RESET is set to the device status register
and a config change intr is sent to the guest driver.
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Hao Li <hao.l.li@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Virtio modern changed the virtqueue cofiguration precedures. GPA
of descriptor table, available ring and used ring are written to
common configuration registers separately. A final write to
Q_ENABLE register triggered initialization of the virtqueue on
the backend device.
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Hao Li <hao.l.li@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This patch implements the read/write callbacks for the registers in the
device-specific region. This region is implemented in the modern MMIO
bar.
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Hao Li <hao.l.li@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This patch implements the read/write callbacks for the registers in the
common configuration region. This region is implemented in the modern
MMIO bar.
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Hao Li <hao.l.li@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This patch implements the generic PCI barread/barwrite callbacks.
Specific barread/barwrite interfaces are called based on the baridx.
Virtio legacy devices, transitional devices and modern devices can
be handled in an unified way.
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Hao Li <hao.l.li@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
virtio_set_modern_bar is an external interface that backend virtio
driver can call to initialize the PCI capabilities and PCI bars
defined in the virtio 1.0 spec.
The following are done in the function:
- 5 PCI capabilities are added to the PCI configuration space of the
virtio PCI device. (common/isr/device_specific/notify/cfg_access)
- A 64-bit MMIO bar is allocated to accommodate the registers defined
in the 4 PCI capabilities. (cfg_access capability does not require
MMIO.)
- If use_notify_pio is true, a PIO notify capability is added to the
PCI configuration space and a PIO bar is allocated for it
accordingly.
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Hao Li <hao.l.li@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Struct virtio_base and struct virtio_vq_info are expanded to support
virtio 1.0 framework. The BAR layouts of virtio legacy/transitional/
modern are introduced as well.
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Hao Li <hao.l.li@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
New compiler options introduced by commit
519c4285cf will cause DM compile failure
which caused by warnings from some snprintf usage might be truncated.
Expanding the string buffer to make compiler happy.
v3: change format string
v2: Address comment from Hao, shrink bident string size to satify
tname length in blockif_open.
Signed-off-by: Rusty Lynch <rusty.lynch@intel.com>
Signed-off-by: Liu Shuo <shuo.a.liu@intel.com>
