Commit Graph

10 Commits

Author SHA1 Message Date
Victor Sun
401ffd1e39 HV: pm: cleanup for misra integral type violations
The patch fixes integral type related violations on HV pm part.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-07-12 17:31:11 +08:00
Zide Chen
92cd2612fc hv: fixup addresses in the c code for relocation
- Trampoline code doesn't have the same relocation delta with HV,
  Need to manually patch them when referenced from HV
- replace all references to CONFIG_RAM_START with the actual HV load
  address

Signed-off-by: Zheng Gen <gen.zheng@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-07-11 10:25:16 +08:00
Junjie Mao
3956ce1596 HV: io: spell out explicit narrowing of integers
The MMIO/PIO write APIs in io.h always take a uint32_t value but may uses it as
8, 16 or 32-bit integers. This patch converts the prototypes to align with their
functionality.

The pointer conversion and assignment are splitted to separate statements to
prevent static checkers from being confused about the underlying types.

v1 -> v2:

    * Change the prototype of mmio-related functions, instead of keeping the
      explicit conversions internal. The addresses are kept void* since in most
      cases hva (in void*) is passed.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-10 13:10:10 +08:00
Yonghua Huang
cc7167026b HV: cleanup coding style violation
- replace MACROs with inline functions
 - remove unused local viarbles
 - fix build errors

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-07-05 10:00:14 +08:00
Huihuang Shi
2ffa69cb9a HV:misc:fix "signed/unsigned conversion without cast"
Misra C required signed/unsigned conversion with cast.

V1->V2:
  a.split patch to patch series

V2->V3:
  a.change the uint64_t type numeric constant's suffix from U to UL

Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-07-04 12:18:38 +08:00
Yin Fengwei
5b43521461 hv: trap vm0 write/read pm1a/pm1b registers
ACRN needs to trap the pm1a/pm1b written/read from VM0. So we
could know when should we put the system to S3.

We will have two path back to VM0:
 - S3 enter/exit sucess. Will reset VM0 and jump to VM0 wakeup vec
   with real mode
 - S3 enter/exit failed. Will return to the next instruction of
   pm1a/pm1b register writing. VM0 will read the pm1a/pm1b evt
   register to check whether it's waked up or not.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-29 00:50:01 +08:00
Yin Fengwei
0f9d9641d4 hv: add function to return to VM0
Emulate VM0 resume from S3 state:
 - reset BSP of VM0
 - set the BSP entry to saved VM0 wakeup vec and set BSP to real mode
 - start BSP

To match trampoline_spinlock release on ACRN Sx resume path, acquire
trampoline_spinlock if ACRN Sx enter fails.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-29 00:50:01 +08:00
Yin Fengwei
02d819144e hv: add enter_s3
enter_s3 is main function for ACRN to enter S3 state with following
process:
 - pause vm0
 - save the wakeup vec of vm0 and set wakeup vec of ACRN. So
   resume from S3 will jump to ACRN wakeup
 - offline APs
 - update the main entry of trampoline to resume entry. After BSP
   is resume from S3, it will jump to resume entry instead of AP
   startup routine
 - turn off vmx
 - suspend devices
 - enter S3.

exit S3 with following process:
 - release trampoline_spinlock which is hold in trampoline code
 - resume devices
 - enable vmx
 - update the main entry of trampoline to AP startup routine.
 - online APs.

The following operations will be resume vm0 which will be added
in next patch.

Signed-off-by: Zheng Gen <gen.zheng@intel.com>
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-29 00:50:01 +08:00
Yin Fengwei
a06a2f28cd hv: implement lowlevel S3 enter/wakeup
The S3 enter lowlevel routine saves the cpu context to memory
and enter S3 state

The S3 wakeup lowlevel routine restore cpu context and return.

Signed-off-by: Zheng Gen <gen.zheng@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-29 00:50:01 +08:00
Yin Fengwei
74dfa425e0 hv: Add initialize pm.c
Now, we only add native msr save/restore functions. The native power
related functions will be put to this file.

Signed-off-by: Zheng Gen <gen.zheng@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-06-14 13:41:45 +08:00