Commit Graph

751 Commits

Author SHA1 Message Date
Mingqiang Chi
60c05ace1a hv:Replace vlapic pointer with instance in vcpu_arch
-- update 'vlapic' in 'struct vcpu_arch' from pointer
   to instance
-- add inline function(vcpu_vlapic) in vcpu.h

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-12 09:20:07 +08:00
Mingqiang Chi
aae5018bec hv:Move vlapic structure to vlapic.h
move structure vlapic_pir_desc/vlapic_timer/
acrn_vlapic from vlapic_priv.h to vlapic.h

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-12 09:20:07 +08:00
Mingqiang Chi
fdb64095c4 hv:Replace dynamic memory allocation for apic access address
Replace pointer with static memory for apicv_apic_access_addr

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-12 09:20:07 +08:00
Mingqiang Chi
887ebf0b08 hv: Replace dynamic memory allocation for MSR bitmap
Replace pointer with static memory for msr_bitmap
inside structure vm_arch.

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-12 09:20:07 +08:00
Mingqiang Chi
02e7edc063 hv: Replace dynamic memory allocation for I/O bitmaps
-- Replace pointer with static memory for io_bitmap
  inside structure vm_arch.
-- Refine allow_guest_pio_access/deny_guest_pio_access

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-12 09:20:07 +08:00
Mingqiang Chi
eada04b800 hv:Replace dynamic memory allocation for vmcs region
Replace vmcs pointer with static memory for vmcs region
inside structure vcpu_arch.

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-12 09:20:07 +08:00
Yin Fengwei
bca43b5324 hv: avoid memory leak in trampoline code preparing
In function start_cpus, we allocated memory under 1M when
preparing AP trampoline code.

With S3 feature enabled, start_cpus is called every time after
ACRN resume from S3 which leaks the allocated memory for AP
trampoline code.

To avoid memory leak, move the AP trampoline preparing function
out of start_cpus to make sure the memory for AP trampoline is
only allocated one time when system boot.

Tracked-On: #1156
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Zide Chen <zide.chen@intel.com>
2018-09-11 13:00:54 +08:00
Shiqing Gao
bcaede0c0e hv: treewide: fix 'Use of function like macro'
- convert function like macros to inline functions based on MISRA-C
  requirement
- remove some unused and duplicated macros

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-09-11 10:49:48 +08:00
Jason Chen CJ
d72e65c91a trusty: do not destroy secure world if it's not created
check sworld_eptp before real destroy_secure_world

Tracked-On: #1200
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-09-11 10:47:34 +08:00
Jason Chen CJ
8773dfb1f6 vlapic: unmap vlapic base only for SOS
as SOS mapped all memory at the beginning, so trap vlapic need unmap its
memory; for UOS, there is no need as UOS never mapped it.

Tracked-On: #1124
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-09-11 10:47:34 +08:00
Jason Chen CJ
457ac7408d vcpu: replace start_vcpu with run_vcpu
run_vcpu should be a more suitable name

Tracked-On: #1199
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-09-11 10:47:34 +08:00
Jason Chen CJ
2978c01f45 io: tiny fix for error message
error message for "read" or "write" was incorrect.
for developers, we just need print out direction & type value.

Tracked-On: #875
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-09-11 10:47:34 +08:00
Minggui Cao
99285f844a HV: improve pass-thru device interrupt process
for each pass-thru device and its entry owned by one VM, so
change the pass-thru device's softirq lock & entry list into
per VM, so one VM's PT device interrupt process will not
interfere with other VMs; especially in case one user OS
"interrupt storm" happens, it will have little effect on
service OS.

Tracked-On: #866
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-10 10:12:45 +08:00
Yu Wang
b4e03f2d68 hv: virq: make irq_window_enabled useful
The arch_vcpu->irq_window_enabled is almost useless in original code.
This patch use it to avoid unnecessary "interrupt-window exiting"
conditions check if "interrupt-window exiting" is aleady enabled.

Tracked-On: #1190
Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-10 10:12:18 +08:00
Yu Wang
8e296155d5 hv: apicv: enable interrupt-window if any pending external interrupts
The external interrupt events only can be inject if RFLAGS.IF = 1 and no
blocking by both STI and MOV SS. If met this scenario, we need to enable
"interrupt-window exiting" for injection in next VMEXIT.

Tracked-On: #1189
Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-10 10:12:18 +08:00
Yu Wang
46c3276ec8 hv: apicv: avoid enable interrupt window if interrupt delivery enabled
If the "virtual-interrupt delivery" is enabled for vmx apicv, then need
avoid to enable interrupt-window exiting. From SDM Vol3, 29.2.1, the
evaluation of pending virtual interrupts only be trigger if
"interrupt-window exiting" is 0.

The original code will enable interrupt-window vmexit if any pending
vlapic interrupts even the "virtual-interrupt delivery" is enabled. It
will cause the pending interrupts can't be evaluate immediately until
guest triggered interrupt-window vmexit.

For "virtual-interrupt delivery" enabled case, just need sync the
pending interrupts to irr and update rvi if needed. And CPU will
evaluate and automatic injecct virtual interrupt at appropriate time. It
doesn't rely on interrupt-window vmexit.

For "virtual-interrupt delivery" disabled case, need to check if satisfy
the virtual interrupt injection conditions before doing the interrupt
injection. If not, then need to enable interrupt-window vmexit and
re-check the conditions in the next time vmexit.

Tracked-On: #1187
Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-10 10:12:18 +08:00
Shiqing Gao
97aeb7f4ff hv: pgtable: fix 'Use of function like macro'
Convert HPA2HVA, HVA2HPA, GPA2HVA and HVA2GPA to inline functions.

v1 -> v2:
 * Modify the following statement.
   rsdp = biosacpi_search_rsdp((char *)hpa2hva((uint64_t)(*addr << 4)),
                                                                0x400);
   Instead of "(uint64_t)(*addr << 4)", "(uint64_t)(*addr) << 4U" would
   be clearer.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-09-07 11:11:06 +08:00
Mingqiang Chi
5c5aed6188 hv:Change several VMX APIs to void type
-- Change vmx_off/exec_vmxon/exec_vmclear/exec_vmptrld/
  exec_vmxon_instr/init_vmcs to void type
-- for vmxon/vmclear/vmptrld, add pre-conditions to
   guarantee sucessful execution.

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-07 10:23:04 +08:00
Mingqiang Chi
e4e38e1bfb hv:Check if VMX capability is locked with incorrect value
Check if the VMX capability is locked with incorrect value,
at the time when HV do the hardware capability detect.

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-07 10:23:04 +08:00
Mingqiang Chi
65930809ee hv: Replace dynamic allocation with static memory for vmxon_region
Remove vmxon_region_pa from structure per_cpu_region,
and define vmxon_region inside per_cpu_region.

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-07 10:23:04 +08:00
Shiqing Gao
4360235edf hv: treewide: fix 'Macro parameter not in brackets'
Add the brackets for Macro parameter to avoid the unintentional
mistakes.

A simple example that may cause mistakes:
        #define minus(x) -x
When the following call is made,
        z = minus(a-b)
it becomes:
        z = -a-b;
where "-a - b" is equivalent to "(-a) - b" rather than "- (a - b)", as
expected.

v2 -> v3:
 * convert DMAR_WAIT_COMPLETION to inline function
 * remove the macro PIC_PIN_FOREACH and implement the well-formed
   for loop in each case
 * replace __CPP_STRING with STRINGIFY and remove the unused CPP_STRING

v1 -> v2:
 * Remove some changes to function like macro since MISRA-C requires to
   use inline functions if it is possible.
   These MACRO brackets violations will be fixed together when fixing
   other issues related to function like macro.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2018-09-07 10:22:00 +08:00
Mingqiang Chi
1b334ec08f hv: replace 'return' with 'panic' in bsp_boot_post
If hardware_detect_support() failed,as it return to
bsp_boot_init with a different stack and thus returning
from bsp_boot_init becomes an undefined behavior.

Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-06 12:07:26 +08:00
Shiqing Gao
f2f719cfa8 hv: fix 'Procedure is not called or referenced in code analysed'
MISRA-C requires that each function defined and declared shall be called
or referenced in code analyzed.

In some cases, we would like to keep the non-called functions for code
completeness, such as
vcpu_inject_extint/vcpu_inject_nmi/vcpu_inject_gp/vcpu_inject_pf
/vcpu_inject_ud/vcpu_inject_ac/vcpu_inject_ss.

This pacth removes some functions that are independent and are not
called in our code base.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-09-06 12:01:30 +08:00
Shiqing Gao
67038794af hv: treewide: convert some MACROs to inline functions
MISRA-C requires that each parameter in the MACRO shall be in brackets.

In some cases, adding brackets for all of the parameters may not be a
perfect solution.
For example, it may affect the code readability when there are many
parameters used in the MACRO.
And duplicated brackets will appear when one MACRO called another MACRO
which is using same parameters.

This patch convert some MACROs to inline functions to avoid such cases.

v1 -> v2:
 * Remove the unnecessary changes in hypervisor/bsp/uefi/efi/boot.h

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-09-04 12:27:18 +08:00
Shiqing Gao
54439ecae1 hv: treewide: fix 'Expression is not Boolean'
MISRA-C requires that the controlling expression of an if statement or
an iteration-statement shall be Boolean type.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-09-03 11:23:53 +08:00
Kaige Fu
f611012d28 HV: Refine two log info about vcpu and instr_emul
We have two same log message in decode_instruction. It's a little bit confusing.
So, this patch refine the log message to make it more explicit.

BTW, we refine one message in create_vcpu.

Tracked-On: #1136

Signed-off-by: Kaige Fu <kaige.fu@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-03 11:23:15 +08:00
Shiqing Gao
96dba0d8fe hv: fix MISRA-C issues related to space or newline
This patch fixes the following issues:
- No newline after semi colon.
- No space after semi colon in for expression.
- No space between if, while, for and expresn.

v1 -> v2:
 * Fix the typo for the for loop change.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2018-09-03 09:35:15 +08:00
Li, Fei1
d67eefb012 hv: mmu: use get/set_pgentry to get/set page table entry
And remove mem_read/write_xx API.

Tracked-On: #1124

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-03 09:32:49 +08:00
Li, Fei1
7f9befb643 hv: ept: remove find_next_table
We don't need find_next_table to walk to the next EPT page table.

Tracked-On: #1124

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-03 09:32:49 +08:00
Li, Fei1
9257ecf4bb hv: mmu: cleanup mmu.h
Remove unused Macro defininion.

Tracked-On: #1124

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-03 09:32:49 +08:00
Li, Fei1
06ab2b829f hv: mmu: add 1GB page capability check when CPU boot
Add 1GB large page support limit on our platform.

Tracked-On: #1124

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-03 09:32:49 +08:00
Li, Fei1
58fffcd3b9 hv: mmu: rename PTT_HOST to PTT_PRIMARY
Tracked-On: #1124

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-09-03 09:32:49 +08:00
Sainath Grandhi
c102c44c16 hv: Device MSIs in partition mode ACRN
VMs in partition mode uses a kernel patch to switch to physical mode xAPIC.
The kernel patch together with this patch makes sure device MSIs use
physical mode as DM and physical APIC IDs in Destination field.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-09-03 09:32:15 +08:00
wenshelx
25dacc5c19 security: Enable '-fpie, -pie' options
To be sure hypervisor and DM are position independent
and executable.

Tracked-On: #1122
Signed-off-by: wenshelx <wenshengx.wang@intel.com>
Acked-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
2018-08-31 11:18:26 +08:00
Shiqing Gao
10c64a5fca hv: fix MISRA-C issues related to for loop
This patch fixes the following issues:
- Assignment operation in expression.
- For loop incrementation is not simple.
- No brackets to loop body.
- Use of comma operator.

v1 -> v2:
 * Replace &x->y with &(x->y) based on our new coding rule

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2018-08-31 09:20:48 +08:00
Sainath Grandhi
43741ba5e3 hv: Leave interrupts disabled during vmexit - ACRN partition mode
Since vmexit handling in ACRN partition mode is not complex (since no SOS and
all devices passthru), interrupts can stay disabled in root mode during
vmexit handling.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-31 08:48:47 +08:00
Mingqiang Chi
12c16876da hv:No need to create inverted page tables for trusty memory
There is no requirement to  hpa2gpa for trusty memory,
now we use the same inverted eptp for normal world and secure world,
that is it can get some trusty memory information by the inverted
page tables in normal world,then this patch removed the inverted
page tables for trusty memory.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-29 09:10:45 +08:00
Shiqing Gao
2a184f353c hv: code clean up regarding to guest_msrs
Change guest_msrs in vcpu data structure from pointer to array, which
could avoid the dynamic memory allocation.

v1 -> v2:
 * Remove the unnecessary initialization for guest_msrs[] since vcpu is
   allocated by calloc.

Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-28 11:08:48 +08:00
Victor Sun
947e86db09 HV: restore correct gpa for guest normal world
We should specify gpa for uos or sos when restore memory, otherwise
it would cause resume failure issue.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2018-08-28 09:45:32 +08:00
Mingqiang Chi
4e8798e018 hv:Replace vioapic pointer with instance in structure vm
-- rename struct vioapic --> struct acrn_vioapic
-- update 'vioapic' field in 'struct arch_vm' from pointer
   to instance
-- change vm_ioapic(vm) to inline, and move it to vm.h
-- change vioapic_init to void type

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-27 09:49:12 +08:00
Mingqiang Chi
29dbd1084d hv:Replace vuart pointer with instance in structure vm
-- update 'vuart' field in 'struct vm' from pointer
   to instance
-- replace MACRO with inline function for vm_vuart,
   and move it to vm.h
-- change vuart_init to void type
-- rename struct vuart -->struct acrn_vuart

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-27 09:49:12 +08:00
Mingqiang Chi
0b54946bac hv:Replace vpic pointer with instance in structure vm
-- update 'vpic' field in 'struct vm' from pointer
  to instance, and move it from 'struct vm' to 'struct arch_vm'
-- replace MACRO with inline function for vm_pic, and move it
   to vm.h
-- changed vpic_init to void type
-- removed vpic_cleanup
-- move struct acrn_vpic/i8259_reg_state from vpic.c to vpic.h

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-27 09:49:12 +08:00
Yang, Yu-chu
de53964c05 HV: Removed the unused parameters and union from gdt
In the gdt.h, it defines unions and parameters which is not used
in hypervisor. Removed them to keep the gdt definition simple.

Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-27 09:40:25 +08:00
Chen, Gang G
8d35f4e0e8 HV: wrap and enable hkdf_sha256 key derivation based on mbedtls
Derive multiple seeds to support multiple guest VMs

Signed-off-by: Chen, Gang G <gang.g.chen@intel.com>
2018-08-27 09:39:05 +08:00
Sainath Grandhi
925503ce36 hv: Build fix - ACRN partition mode
Patch to fix compile issue.

Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
2018-08-24 11:17:33 +08:00
Yonghua Huang
7bc1a3f925 HV: Refine APICv capabilities detection
- by default, ACRN will not support platform without
   below APICv features:
    -- Use TPR shadow
    -- APIC-register virtualization

 - remove mmio emualtion of local APIC for guest

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-24 09:58:58 +08:00
Binbin Wu
f95d07dc43 hv: vtd: use EPT as translation table for PTDev in SOS
In current code, the address translation type for passthrough devices
in SOS is passthrough type, which means the device in SOS can access
the whole physcial memory.
This patch uses SOS EPT to translate address for passthrough
devices. So that the memory of VMM or trusty can be protected from
SOS PTDev.

Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-08-23 11:46:57 +08:00
Yin Fengwei
4579e57e7b hv: add gva check for the case gva is from instruction decode
For the instructions other than MOVS, one operand is register
and another one is memory which trigger EPT voilation. In this
case, there is one possibility that EPT voilation happens before
guest fault:
    the fault is triggered by related guest PTE access bit
    voilation (like write to a gva with R/W bit cleared in PTE).

So we do this kind of check and inject exception to guest
accordingly during instruction decoding phase.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00
Yin Fengwei
7dde0dfa4b hv: add GVA validation for MOVS
Unlike the other instructions we emulated, MOVS has two operands
both are memory.

So we need to check whether the operand is valid GVA. With VMX
enabled, the src operand is always checked first by VMX. Which
means if src operand is not valid GVA, it will trigger fault
in guest before trigger EPT. So we don't need to check src
operand. Only need to check dst operand here.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00
Yin Fengwei
b01a81279a hv: add new function to get gva for MOVS/STO instruction
Drop the get_gla function and add
 - get_gva_di_si_nocheck
   get gva from ES:DI and DS(other segment):SI without
   check faulure case
 - get_gva_di_si_check
   get gva from ES:DI and DS(other segment):SI with failure
   case checked

TODO:
  - Save dst_gpa and src_gpa for instruction emulation phase
    use.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
2018-08-23 11:13:48 +08:00