Commit Graph

119 Commits

Author SHA1 Message Date
Mingqiang Chi
51414536fa hv:add suffix(UL)for MACRO(SECURE_WORLD_ENABLED)
Now the MACRO SECURE_WORLD_ENABLED (1<<0)
Change it to 64 bit data
SECURE_WORLD_ENABLED (1UL<<0)

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:26 +08:00
Mingqiang Chi
9aa9a77457 mmu:create temporary page tables for guest at run time
Before this patch, guest temporary page tables were generated by hardcode
at compile time, HV will copy this page tables to guest before guest
launch.

This patch creates temporary page tables at runtime for the range of 0~4G,
and create page tables to cover new range(511G~511G+16M) with trusty
requirement.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:26 +08:00
Zheng, Gen
4d0f26d0e1 UEFI: update acrn.conf and Document
Since the boot flow had been changed to that sos kernel is lanuched
by cl bootloader directly, replace the payload acrn.efi with bzImage.efi
in the acrn.conf file, and specify ROOTDEV with UUID in the command line.

The UEFI firmware launches the EFI/org.clearlinux/bootloaderx64.efi
as os loader not the EFI/BOOT/BOOTX64.EFI, so fix the issue in the document
ACRN_UEFI.txt which guides user with incorrect steps.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
Reviewed-by: Jack, Ren <jack.ren@intel.com>
2018-05-15 17:25:26 +08:00
Qi Yadong
7430074a12 trusty: initialize tsc_offset to zero
Per trusty design, trusty requires a monotonic increasing
secure tick(TSC) at run time. This secure tick will used
to mitigate password/pin force attack, control key expiration,
etc.

Currently, the TSC_OFFSET is enabled. And guest will got
(host_tsc + tsc_offset) when execute rdtsc/rdtscp/rdmsr to
aquire tsc value. The host_tsc is always keeping increasing
during the runtime.

So initialize tsc_offset of trusty to 0 will ensure the
secure tick feature.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:25 +08:00
Jason Chen CJ
bf36022ce9 ept: change eptp to PA
eptp should be record as PA.

this patch changed nworld_eptp, sworld_eptp and m2p eptp to PA type,
necessary HPA2HVA/HVA2HPA transition is used for them after the change.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:25 +08:00
Jason Chen CJ
8682552273 mmu: identify VA and PA in mmu.c
- read/write page table entries should use VA which defined as "void *"
- the address data in page table entries should us PA which defined as
  "uint64_t"

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:25 +08:00
Victor Sun
24ea869e25 HV: add px data of bxt j3455 SOC
The cpu model name of "Intel(R) Celeron(R) CPU J3455 @ 1.50GHz" is used for
APL NUC which is in Acrn official suport list.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:25 +08:00
Victor Sun
7647517a15 HV: trap and validate px request
Currently acrn partitions cpus between SOS and UOS, so the default
policy is to allow guest managing CPU px state. However we would
not blindly passthrough perf_ctrl MSR to guest. Instead guest access
is always trapped and validated by acrn hypervisor before forwarding
to pcpu. Doing so leaves room for future power budget control in
hypervisor, e.g. limiting turbo percentage that a cpu can enter.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:25 +08:00
Victor Sun
1d0d4d3185 HV: add hypercall interface of get vcpu state data
We can use this interface for VHM to pass per-cpu power state data
to guest per its request.

For now the vcpu power state is per-vm, this could be changed if
per-cpu power state support is required in the future.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:25 +08:00
Victor Sun
0e2b9fc7fa HV: setup px info when create vm
The vm px info would be used for guest Pstate control.
Currently it is copied from host boot cpu.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:25 +08:00
Victor Sun
a28fbd15b5 HV: load cpu px data in boot
The patch takes Intel ATOM A3960 as example that hard code all Px info
which is needed for Px control into Acrn HV and load it in boot process.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:25 +08:00
Victor Sun
4cd2717038 HV: add cpu model name
The cpu model name would be used to distinguish which hard coded data
need to be loaded to boot_cpu_data;

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:25 +08:00
Jason Chen CJ
878b5a0466 mmu: refine functions for invept
- rename mmu_invept to invept
- panic if HW doesn't support invept

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-15 17:25:25 +08:00
Jason Chen CJ
a68850e00f mmu: replace ASSERT with panic in fetch_page_table_offset
all callers for fetch_page_table_offset should already make sure
it will not come to an unknown table_leve, so just panic here.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-15 17:25:25 +08:00
Jason Chen CJ
c2f86f23c3 mmu: refine functions walk_paging_struct & update_page_table_entry
- walk_paging_struct should return sub_table_addr, if something wrong,
  it return NULL
- update_page_table_entry should return adjusted_size, if something wrong
  it return 0

the change is valid under release version, as at that time, ASSERT in
walk_paging_struct is empty.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:25 +08:00
Jason Chen CJ
bb82504f05 mmu: refine functions get_table_entry & obtain_last_page_table_entry
- remove unused map_params in get_table_entry
- add error return for both, which is valid under release version,
  as at that time, ASSERT in get_table_entry is empty.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:25 +08:00
Jason Chen CJ
cbcc7c0db3 mmu: refine function break_page_table
function break_page_table should return next_level_page_size, if
something wrong, it return 0.

the change is valid for release version, as at that time ASSERT()
in break_page_table is empty.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:25 +08:00
Jason Chen CJ
6454c7be6b mmu: refine function map_mem_region
function map_mem_region should return mapped_size, if something wrong,
it return 0.

the change is valid for release version, as at that time ASSERT()
in map_mem_region is empty.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:25 +08:00
Jason Chen CJ
fa3e424fcf mmu: refine functions modify_paging & map/unmap/modify mem
add error return for all, which is valid under release version,
as at that time, ASSERT in modify_paging is empty.

Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:25 +08:00
Jack Ren
ec1cbbb660 UEFI: get the guest entry address explicitly
Previously with the help from gcc, __builtin_return_address(0) is
used as the guest entry address, but it can't work well with gcc 7.3
and leads to the guest unable to return to UEFI correctly.
Let's get it explicitly.

Signed-off-by: Jack Ren <jack.ren@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:25 +08:00
Geoffroy Van Cutsem
c5c4b63150 Travis CI: enable Ubuntu 16.04 and Fedora 26 testing
Enable compilation test for Fedora 26 and Ubuntu 16.04. The tests
will run for all combinations of RELEASE={0|1} and PLATFORM={sbl|uefi}

Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
2018-05-15 17:25:24 +08:00
Geoffroy Van Cutsem
1ac5a2aebd Enable Travis CI for all combinations
Enable the Travis CI testing for all combinations of variables
that can be set at compile-time. I.e. RELEASE={0|1} and
PLATFORM={0|1}

Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
2018-05-15 17:25:24 +08:00
David B. Kinder
3726a0f7a5 doc: fix hypercall API doxygen errors
Documentation for parameters must match exactly in spelling and case.
Parameter named "vcpu" was incorrectly documented as "VCPU", and
parameter named "param" was documented as "param's".

Signed-off-by: David B. Kinder <david.b.kinder@intel.com>
2018-05-15 17:25:24 +08:00
yechunliang
b11460f7f6 replace malloc and memset with calloc
malloc: allocate a block of memory, the contents of the block are undefined.
calloc: allocate a block of memory for an array of num elements and initializes all its bits to zero.

Signed-off-by: yechunliang <yechunliangcn@163.com>
2018-05-15 17:25:24 +08:00
Mingqiang Chi
92d86383be hv:check continuous hpa when create secure world
Add check_continuous_hpa API:
when create secure world,if the physical
address is not continuous, will assert.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:24 +08:00
Mingqiang Chi
e5be957945 hv:add destroy Secure world API
This patch added API destroy_secure_world, which will do:
-- clear trusty memory space
-- restore memory to SOS ept mapping
It will be called when VM is destroyed, furthermore, ept of
Secure world will be destroyed as well.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:24 +08:00
Li, Fei1
ace23b5088 hv: shell: add cpuid command
Add cpuid shell command for test

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-15 17:25:24 +08:00
Qi Yadong
c83bcded99 trusty: fix typo of comments
Remove TODO comments since it has been done below the comments.
Typo fix: startup_info --> startup_param.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:24 +08:00
Geoffroy Van Cutsem
46bb2dbd51 Add initial .travis.yml and Dockerfile (Clearlinux)
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
Signed-off-by: T <shrmrf@users.noreply.github.com>
2018-05-15 17:25:24 +08:00
Minggui Cao
2db1324837 add vmx msr ops protection from guest OS
1.it doesn't support VMX for guest OS
2.for MSR out of control, inject GP to guest OS.

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:24 +08:00
Mingqiang Chi
5e3dca4c0c hv: free ept memory enhancement
--add free_paging_struct api, used for free page tables
  it will clear memory before free.
--add HPA2HVA translation when free ept memory

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:24 +08:00
Mingqiang Chi
cf7fe07276 hv:bugfix for the API of creating secure world
Before this patch, HV accesses PML4E of secure world when the PML4
doesn't exist,will access null pointer.
Fix as follow:
Before the copy of PDPTE,will allocate memory and write PML4E,
then copy the PDPTE.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Reviewed-by: Anthony Xu <anthony.xu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:24 +08:00
Junjie Mao
f347d15e7d hv: cpu: use the physical address limit from CPUID when available
Per SDM Vol. 2:

    If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address
    number supported should come from this field.

This patch gets the maximum physical address number from CPUID leaf
0x80000008 and calculates the physical address mask when the leaf is
available.

Currently ACRN does not support platforms w/o this leaf and will panic
on such platforms.

Also call get_cpu_capabilities() earlier since the physical address mask
is required for initializing paging.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:24 +08:00
Junjie Mao
cc975f7858 cpu: cache the maximum input value for CPUID extended function
Per SDM:

    When CPUID executes with EAX set to 80000000H, the processor returns
    the highest value the processor recognizes for returning extended
    processor information. The value is returned in the EAX register and is
    processor specific.

This patch caches this value in the global cpuinfo_x86.cpuid_leaves. This
value will be used to check the availability of any CPUID extended
function.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:24 +08:00
Junjie Mao
4542d3775d hypercall: Fix compile error caused by missing memcpy function
Assignment of structures are implemented using memcpy which is not
available in the hypervisor. This patch convert such assignment to an
explicit memcpy_s() call.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:24 +08:00
Minggui Cao
3f03dee3d5 enable TSC-offset & add TSC MSR emulation
enable TSC offset in VMX, so if TSC MSR is changed by guest OS,
write a caculated value into TSC-offset, then host TSC will not be changed.

Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: He, Min <min.he@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:23 +08:00
Yonghua Huang
316731c9a5 hv: pass-through xsave feature to guests
enable Xsave feature and pass-through it to guests
 update based on v2:
  - enable host xsave before expose it to guests.
  - add validation for the value to be set to 'xcr0' before call xsetbv
    when handling xsetbv vmexit.
  - tested in SOS guest, created two threads to do different
    FP calculations,test code runs in user land of sos.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:23 +08:00
Junjie Mao
c01a236efb treewide: fix declarations of functions with empty parameter lists
According to C99:

    The empty list in a function declarator that is not part of a definition of
    that function specifies that no information about the number or types of the
    parameters is supplied.

This means gcc is happy with the following code, which is undesirable.

    void foo();    /* declaration with an empty parameter list */

    void bar() {
        foo();     /* OK */
        foo(1);    /* OK */
        foo(1, 2); /* OK */
    }

This patch fixes declarations of functions with empty parameter lists by adding
an unnamed parameter of type void, which is the standard way to specify that a
function has no parameters. The following coccinelle script is used.

    @@
    type T;
    identifier f;
    @@

    -T f();
    +T f(void);

New compilation errors are fixed accordingly.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:23 +08:00
Jack Ren
c730806a36 version: v0.1-rc3
Signed-off-by: Jack Ren <jack.ren@intel.com>
2018-05-15 17:25:17 +08:00
Jack Ren
8c2dbe1ba4 update home page information
Signed-off-by: Jack Ren <jack.ren@intel.com>
2018-05-15 17:19:39 +08:00
Mingqiang Chi
de5277fb3e hv: Save secure world memory info into vm instead of vm0
A bugfix for saving secure world memory info.
Maybe there are multiple UOS, each VM has its own secure
world and normal world, should save memory info into individual VM.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:19:39 +08:00
Rusty Lynch
80a7dda419 Fix compile error caused by missing memcpy function
On some toolchain configurations direct struct assignments will
default to a memcpy operation which is not present in this
environment, so explicitly use the internal memcpy_s function.

Signed-of-by: Rusty Lynch <rusty.lynch@intel.com>
2018-05-15 17:19:39 +08:00
Zheng, Gen
7a18425780 UEFI: update documentation
Add a new document named ACRN_UEFI.txt to direct user how
to use the acrn.efi.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:19:39 +08:00
Zheng, Gen
e0128b1173 UEFI: add FIXME comments to function emalloc() & __emalloc()
Add a FIXME comment that the emalloc() & __emalloc cannot
guarantee to return address under 4G, and the hypervisor
cannot handle params, which address is above 4G, delivered
from efi stub.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:19:39 +08:00
Zheng, Gen
88b79c901b UEFI: create new func named construct_mbi
Cleanup the mass code for constructing multiboot info

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:19:39 +08:00
Zheng, Gen
2bec3b3c73 UEFI: cleanup functions in boot.c file
Remove the useless function named get_path().
Remove the useless function named print_ch().
Remove the useless function named isspace().
Move the function memory_map() from boot.c to malloc.c

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:19:39 +08:00
Zheng, Gen
bf0d54de0c UEFI: header file cleanup
Move the header content from boot.c to boot.h

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:19:39 +08:00
Zheng, Gen
fde0789ccc UEFI: change the efi_ctx passing method
Save the pointer of efi_ctx in mi_drivers_addr field of
multiboot structure and pass to hypervisor, not by
saving in register RDX(the third default parameter in
64bit call function).

With this method, we can be compatible with the original
32bit boot parameters passing method and no need to
large the array size of boot_regs in hypervisor.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:19:39 +08:00
Zheng, Gen
b240450064 UEFI: change the acrn boot flow on uefi platform
With current code, the acrn.efi is inserted between
cl bootloader.efi and bzImage.efi that destroyed the chain
relationship of cl bootloader and cl bzImage.efi.
And the following is current boot flow:
UEFI -> cl bootloader.efi -> acrn.efi -> bzImage.efi

The purpose of this patch is resume above chain relationship,
and make uefi vm return to efi stub context once launched,
then continue to call the UEFI API(LoadImage/StartImage) to launch
cl bootloader or other bootloaders. So the boot flow will
change to be as below:
UEFI -> acrn.efi -> cl bootloader.efi -> bzImage.efi

After applying this patch, the code related to loading
bzImage.efi and getting pe_entry is unnecessary due to
the bzImage.efi will not be launched by acrn.efi directly,
so it is removed.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:19:39 +08:00
Zheng, Gen
1f3acb3dd9 UEFI: bug fix on delivering RSDP
With current code, memcpy rsdp to 0x500 maybe overwrite uefi
code/data region.

So remove the legacy BIOS deliver method of RSDP, which need copy
the RSDP to EBDA space which is addressed by the 16bit pointer
at 0x40E or upper memory BIOS space 0xe0000-0xfffff. And just
deliver the pointer of RSDP, which is already saved in UEFI system
table, to hypervisor.

Create a function named efi_init() to separate efi initialize code.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:19:39 +08:00