Commit Graph

17 Commits

Author SHA1 Message Date
Li, Fei1
6560ff367c hv: cpu: add cpu_has_cap() API
Add cpu_has_cap API for cpu feature/capability detect instead of
add get_xxx_cap for each feature/capability detect.

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:55 +08:00
Yonghua Huang
9b37e1464c add IO requrest 'req_buf' check before reference
This address maybe invalid if a hostile address was set
in hypercall 'HC_SET_IOREQ_BUFFER'.it should be validated
before using.

Update:
  -- save HVA to guest OS's request buffer in hyperviosr
  -- change type of 'req_buf' from 'uint64_t' to 'void *'
  -- remove HPA to HVA translation code when using this addr.
  -- use error number instead of -1 when return error cases.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:25:27 +08:00
Yonghua Huang
a0b7fb81b4 Add range check for 'vm0_gpa' before creating EPT
Input('vm0_gpa') should be validated when handling
hypercall 'HC_VM_SET_MEMMAP to create EPT for UOS
in 'hcall_set_vm_memmap()' function.
at least 'hpa' range (from 'vm0_gpa') can't overlap
hypervisor memory region.

Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
2018-05-15 17:25:26 +08:00
Rusty Lynch
6e15aee3b0 Fix warning about unused variable
Signed-off-by: Rusty Lynch <rusty.lynch@intel.com>
2018-05-15 17:25:26 +08:00
Mingqiang Chi
9aa9a77457 mmu:create temporary page tables for guest at run time
Before this patch, guest temporary page tables were generated by hardcode
at compile time, HV will copy this page tables to guest before guest
launch.

This patch creates temporary page tables at runtime for the range of 0~4G,
and create page tables to cover new range(511G~511G+16M) with trusty
requirement.

Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:26 +08:00
Victor Sun
1d0d4d3185 HV: add hypercall interface of get vcpu state data
We can use this interface for VHM to pass per-cpu power state data
to guest per its request.

For now the vcpu power state is per-vm, this could be changed if
per-cpu power state support is required in the future.

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
2018-05-15 17:25:25 +08:00
Junjie Mao
4542d3775d hypercall: Fix compile error caused by missing memcpy function
Assignment of structures are implemented using memcpy which is not
available in the hypervisor. This patch convert such assignment to an
explicit memcpy_s() call.

Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2018-05-15 17:25:24 +08:00
Qi Yadong
b124e0da28 trusty: implement hypercall to initialize trusty
UOS_Loader will trigger boot of Trusty-OS by HC_INITIALIZE_TRUSTY.
UOS_Loader will load trusty image and alloc runtime memory for
trusty. UOS_Loader will transfer these information include
trusty runtime memory base address, entry address and memory
size to hypervisor by trusty_boot_param structure.

In hypervisor, once HC_INITIALIZE_TRUSTY received, it will create
EPT for Secure World, save Normal World vCPU context, init
Secure World vCPU context and switch World state to Secure World.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
2018-05-15 17:19:39 +08:00
Qi Yadong
1fd07ba349 trusty: Simulate Secure Monitor Call(SMC) by Hypercall
For ARM, The SMC instruction is used to generate a synchronous
exception that is handled by Secure Monitor code running in EL3.
In the ARM architecture, synchronous control is transferred between
the normal Non-secure state and the Secure state through Secure
Monitor Call exceptions. SMC exceptions are generated by the SMC
instruction, and handled by the Secure Monitor.The operation of
the Secure Monitor is determined by the parameters that are passed
in through registers.

For ACRN, Hypervisor will simulate SMC by hypercall to switch vCPU
State between Normal World and Secure World.
There are 4 registers(RDI, RSI, RDX, RBX) reserved for paramters
passing between Normal World and Secure World.

Signed-off-by: Qi Yadong <yadong.qi@intel.com>
2018-05-15 17:19:38 +08:00
Li, Fei1
936c254d58 Don't use HV_DEBUG outside debug directory
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-15 17:19:37 +08:00
Zheng, Gen
124910ba14 vm load: fix bug in loading kernel
According to the explaination for pref_address
in Documentation/x86/boot.txt, a relocating bootloader
should attempt to load kernel at pref_address if possible.
But due to a non-relocatable kernel will unconditionally
move itself and to run at perf address, no need to copy
kernel to perf_address by bootloader.

Signed-off-by: Zheng, Gen <gen.zheng@intel.com>
2018-05-15 17:19:37 +08:00
Li, Fei1
74e2bfc15f Simple get_vmx_cap()
Don't check MSR Control Features in get_vmx_cap

Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-05-15 17:19:36 +08:00
Mingqiang Chi
cc1d532131 add data structure in vm for enable trusty feature
add key info structure
add sworld_eptp in vm structure, and rename ept->nworld_eptp
add secure world control structure

Change-Id:
Tracked-On:220921
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
2018-05-15 17:19:36 +08:00
Jason Chen CJ
e91b6aa31a retpoline: replace indirect jmp in switch_to function
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-15 17:19:36 +08:00
Yin Fengwei
189329e0de apicv: cancel event injection if vcpu is scheduled out
And re-inject the event after vcpu is scheduled in.

Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
2018-05-15 17:19:36 +08:00
Jason Chen CJ
2cb8ce50c1 decouple hv sw version and api version
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
2018-05-11 14:44:29 +08:00
Eddie Dong
7a3a539b17 initial import
internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085

Signed-off-by: Eddie Dong <eddie.dong@intel.com>
2018-05-11 14:44:28 +08:00