The following tasks are done for both BSP and APs:
- Mask all interrupts
- Disable FPU
- Setup stack
- Jump to the C entry of BSP/AP initialization
Additionally, clear BSS sections during BSP boot before
jumping to the C entry point.
Tracked-On: #8788
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Haicheng Li <haicheng.li@intel.com>
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch provides dummy implementations of functions and data
structures required for the IPI and SMP call on RISC-V.
It serves as a placeholder to ensure RISC-V builds pass and
is not needed for the final merge.
Official implementations are still WIP by other engineers:
- To be provided in the library patchset (by Haoyu):
uint16_t ffs64(uint64_t value);
bool bitmap_test(uint16_t nr, const volatile uint64_t *addr);
void bitmap_clear_lock(uint16_t nr_arg, volatile uint64_t *addr);
void bitmap_clear_nolock(uint16_t nr_arg, volatile uint64_t *addr);
uint64_t atomic_cmpxchg64(volatile uint64_t *ptr, uint64_t old, uint64_t new);
- To be provided in the platform initialization patchset (by Hang):
void wait_sync_change(volatile const uint64_t *sync, uint64_t wake_sync);
bool is_pcpu_active(uint16_t pcpu_id);
uint16_t get_pcpu_id(void);
----------
Changelog:
* Split per_cpu.h implementation into a separate commit.
Tracked-On: #8786
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Since smpcall depends on the per_cpu_region data structure to access
smp_call_info_data, this patch adds the initial version of per_cpu
support on RISC-V. For now it only includes SMP call related info.
Further refinement will be done in the platform initialization patchset
(by Hang).
Tracked-On: #8786
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch:
- abstracts the common logic from existing x86 implementation
- moves x86-specific logic to arch/x86/notify.c
A new common/notify.{c,h} is introduced to provide a common SMP call framework for
multi-arch support in ACRN.
arch-specific files such as arch/{x86,riscv}/notify.c is aim to provide the
corresponding implementations respectively.
The framework provides the following common APIs:
- init_smp_call(): initialize the SMP call support during pCPU initialization
- handle_smp_call(): execute the SMP call notification handler
- smp_call_function(): trigger the SMP call request to target pCPUs
Other SW modules should invoke these common APIs to perform arch-independent
SMP operations.
Two arch-specific hooks are abstracted:
- arch_smp_call_kick_pcpu():
- On x86, special handling is required when LAPIC is passthrough.
- On RISC-V, a plain IPI is sufficient to kick the target pCPU.
- arch_init_smp_call():
- On x86, CPU initialization reserves dedicated vectors and
registers callback handlers for purposes such as notifications
or posted interrupts.
- On RISC-V, no special handling is required at present; this
can be extended in the future if needed.
----------
Changelog:
* Merged the following two patches into one:
[RFC PATCH v2 4/7] hv: introduce common/smp.{c,h}
[RFC PATCH v2 5/7] hv: smpcall: x86: adapt to common SMP call
Tracked-On: #8786
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Rename send_single_ipi() and send_dest_ipi_mask() to
arch_send_single_ipi() and arch_send_dest_ipi_mask() in x86, to make the
naming consistent with the RISC-V implementation and reflect that these
functions are arch-specific.
Tracked-On: #8786
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Align the prototype of send_dest_ipi_mask() on x86 with the RISC-V
definition. dest_mask is updated from uint32_t to uint64_t:
From: void send_dest_ipi_mask(uint32_t dest_mask, uint32_t vector)
To: void send_dest_ipi_mask(uint64_t dest_mask, uint32_t vector)
On RISC-V, send_dest_ipi_mask() is implemented using SBI interfaces,
where the dest_mask is defined as "unsigned long" in the SBI spec.
Tracked-On: #8786
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch implements the IPI for RISC-V using SBI interface.
There is no common IPI concept abstracted, due to the following reasons:
- RISC-V:
Software delivers an IPI to target CPUs via software interrupts.
The interrupt number is fixed for each privilege mode (e.g.,
Supervisor Software Interrupt = IRQ 1, Machine Software Interrupt = IRQ 3).
The actual purpose of the IPI is indicated by an IPI message type,
which is a software-level concept. When the IPI is received,
the target CPU must check the message type to determine the required action.
- x86:
Software delivers an IPI to target CPUs using a specific vector number.
During CPU initialization, software can assign dedicated vectors for
particular purposes. When the IPI is received, the target CPU could
directly invoke the handler bound to that vector.
Each architecture provides its own IPI implementation, and other SW modules
directly call these arch-specific functions.
------
Notes:
* To ensure RISC-V builds pass, an empty `include/arch/riscv/asm/cpu.h`
is added since `debug/logmsg.h` includes `asm/cpu.h`.
* Implemented IPI functionality using the SBI IPI Extension (EID #0x735049).
Legacy SBI extensions are not supported in ACRN.
----------
Changelog:
* Updated commit message and code comments to state explicitly that
legacy SBI extensions are not supported in ACRN.
* Refined the prototype of sbi_send_ipi() to align with the SBI spec:
From: int64_t sbi_send_ipi(uint64_t mask)
To: int64_t sbi_send_ipi(uint64_t mask, uint64_t mask_base)
In ACRN it is invoked as sbi_send_ipi(dest_mask, 0UL), with mask_base
set to 0UL.
* Renamed send_single_ipi() and send_dest_ipi_mask() to
arch_send_single_ipi() and arch_send_dest_ipi_mask() respectively.
Tracked-On: #8786
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This patch implements the common SBI interfaces, including
sbi_ecall(), common macros and data structures.
Changelog:
* Renamed SBI_EXPERIMENTAL_x and SBI_VENDOR_x.
* Added description for sbi_ecall().
* Renamed SBI-related enums, macros, and data structures to align with
the SBI specification.
Tracked-On: #8786
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
This commit adds riscv build skeleton and adds some dummy files that
prints out hello world.
To build riscv acrn.out/acrn.bin, simply:
make hypervisor \
BOARD=<any existing board> \
SCENARIO=<any existing scenario> \
ARCH=riscv
We still need to specify board and scenario as those were required by
project level makefile.
Tracked-On: #8782
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
The common files for now contains x86 specific code and needs
refactoring. To increase parallelism, we temporarily confine the common
files to x86 architecture while we tried to enable riscv architecture.
As we progress, this workaround should be completely reverted in future
milestones when we moved all common files to actual common scope.
Tracked-On: #8782
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Currently ACRN supports only x86 architecture. And this patch is the
first of a series of patches to enable ACRN on multiple architecture.
This commit does the multi-arch of Makefile: put x86 specific content
into arch/x86/Makefile.
This includes:
- Pre-launched VM ACPI binary generation
- acrn.32.out generation (32 bit ELF was generated towards i386
architecture)
- Customized modularization (*_MOD). Only one module is created in
common section: COMMON_MOD
- Architecture specific make targets and pre-build actions are moved to
architecture specific makefile. Introduce the following variable to
register arch targets and/or actions:
- ARCH_PRE_BUILD_TARGETS
- ARCH_ALL_TARGETS
- ARCH_INSTALL_TARGETS
Tracked-On: #8782
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
Mark hypervisor memory region as unusable in its e820 table to avoid
being overlapped by e820_alloc_memory(). As it is already filtered out
in hypervisor e820 table, there is no longer need to filter it out in
service VM e820.
Tracked-On: #8738
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
The hypervisor image size is determined at link time, but now it is
calculated and stored in a global variable during mmu initialization,
and the helper function reads from that variable. Change to calculate
it inside helper function to avoid inconsistency.
Tracked-On: #8738
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
The VM-exit instruction length(VMX_EXIT_INSTR_LEN) in VMCS is undefined
on EPT violation, except during delivery of a software interrupt,
privileged software exception, or software exception[1]. Although CPU
is likely to set the field, it can be incorrect in certain cases, such
as cmp+jcc and test+jcc.
Since hypervisor does not know exactly how much bytes needed, and GVA
translation is costly, it first copies at most 15 (VIE_INST_SIZE) bytes
within the page, then decodes the instruction. If more bytes are needed
during decoding and copied length is less than 15, it copies remaining
bytes.
[1] 29.2.5, https://cdrdv2-public.intel.com/671200/325462-sdm-vol-1-2abcd-3abcd.pdf
Tracked-On: #8756
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
The Access Size field in ACPI GAS was not introduced before ACPI 2.0,
Errata C. It is not guaranteed to be a non zero value, like QEMU
programs it to 0. As it only indicates how many bytes it can be
accessed at once, the register size should be determined by Bit Width
and Bit Offset. In IO space, Bit Offset is always 0, the size is
(Bit Width / 8).
Tracked-On: #8771
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@intel.com>
Reviewed-by: Li Fei <fei1.li@intel.com>
In current code process, hyperv data in struct vm_arch is never cleared
during VM shutdown and is retained to next VM launch. As the enabled
bit of hypercall_page msr is not clear, hypercall page might cause fatal
error such as Windows VM BSOD during VM restart and memory
remapping. Hyperv page destory function can ensure hyperv page is
destory during each VM shutdown so hyperv related config such as
hypercall page is established correctly during each VM launch.
Tracked-On: #8755
Signed-off-by: Yichong Tang <yichong.tang@intel.com>
GAI Tooling Notice: These contents may have been developed with support from one
or more generative artificial intelligence solutions.
This patch is to add doxygen style comments for some elements in
vp-dm_vperipheral ivshmem module.
Tracked-On: #8665
Signed-off-by: Haiwei Li <haiwei.li@intel.com>
This patch fixes the following compilation error when including
`release/uart16550.c` into the module test.
./release/uart16550.c:14:6: error: conflicting types for ‘get_pio_dbg_uart_cfg’; have ‘bool(uint64_t *, uint64_t *)’ {aka ‘_Bool(long unsigned int *, long unsigned int *)’}
14 | bool get_pio_dbg_uart_cfg(__unused uint64_t *pio_address, __unused uint64_t *nbytes) {
| ^~~~~~~~~~~~~~~~~~~~
./include/debug/uart16550.h:142:6: note: previous declaration of ‘get_pio_dbg_uart_cfg’ with type ‘bool(uint16_t *, uint32_t *)’ {aka ‘_Bool(short unsigned int *, unsigned int *)’}
142 | bool get_pio_dbg_uart_cfg(uint16_t *pio_address, uint32_t *nbytes);
| ^~~~~~~~~~~~~~~~~~~~
Tracked-On: #861
Signed-off-by: Gao, Shiqing <shiqing.gao@intel.com>
Add reset_control in acrn_vm. Use this reset_control to simulate
RESET_CONTROL(0xCF9) register in hypervisor.
Tracked-On: #8724
Signed-off-by: Yuan Lu <yuan.y.lu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Service VM may write 0x6 to port 0xcf9 to trigger a warm reset, but
current hypervisor always performs a cold reset by writing 0xE to CF9.
Hypervisor should reboot the system in the same mode as Service VM
specified. Specific OS features (like linux pstore) requires warm
reset to keep data across reboot.
The behavior of hv console's reboot command (cold reset) remains
unchanged.
Tracked-On: #8539
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Per SDM, VPDPBUSD/VPDPBUSDS/VPDPWSSD/VPDPWSSDS instructions depend on
CPUID Feature Flag 'AVX-VNNI, AVX512_VNNI, AVX512VL'. 'AVX512_VNNI' and
'AVX512VL' are already exposed to any VM.
'AVX-VNNI' is in CPUID.(EAX=07H,ECX=1):EAX.AVX-VNNI[bit 4]. This patch
is to expose all the CPUID.EAX=07H subleaf features to VMs.
Mask corresponding bits if want to disable some features in the future.
Tracked-On: #8710
Reviewed-by: Fei Li <fei1.li@intel.com>
Signed-off-by: Haiwei Li <haiwei.li@intel.com>
GAI Tooling Notice: These contents may have been developed with support from one
or more generative artificial intelligence solutions.
This patch is to add doxygen style comments for some elements in
vp-dm_vperipheral vhost_bridge module.
Tracked-On: #8665
Signed-off-by: Haiwei Li <haiwei.li@intel.com>
A vhostbridge can be emulated in hypervisor. Function `init_vhostbridge()` is
used to initialize a virtual host bridge and it configures the PCI configuration
space.
However, some configuration elements are not clearly described, which affects
maintainability and readability. This patch add some comments to address it.
Tracked-On: #8665
Signed-off-by: Haiwei Li <haiwei.li@intel.com>
Remove unreachable code branch in line 163:
if CR0 enabled WP, supervisor-mode writing a read-only page have
been checked in line 109.
Merge redundant checking:
if smap is enabled, supervisor-mode can't access user-mode address
when eflags.ac disabled.
Tracked-On: #8708
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Some hypercalls return -ENODEV which should be set into RAX as return
value, e.g. HC_ASSIGN_PCIDEV. So, remove the check in
vmcall_vmexit_handler() and change return value to -EACCESS if the
hypercall is not sent from Service VM or allowed VM.
Tracked-On: #8598
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
GAI Tooling Notice: These contents may have been developed with support from one
or more generative artificial intelligence solutions.
This patch is to add doxygen style comments for some elements in
vp-dm_vperipheral vuart module.
Tracked-On: #8665
Signed-off-by: Haiwei Li <haiwei.li@intel.com>
GAI Tooling Notice: These contents may have been developed with support from one
or more generative artificial intelligence solutions.
This patch is to add doxygen style comments for some elements in
vp-dm_vperipheral vpci_bridge module.
Tracked-On: #8665
Signed-off-by: Haiwei Li <haiwei.li@intel.com>
GAI Tooling Notice: These contents may have been developed with support from one
or more generative artificial intelligence solutions.
This patch is to add doxygen style comments for some elements in vp-dm_vperipheral
vrtc module.
Tracked-On: #8665
Signed-off-by: Haiwei Li <haiwei.li@intel.com>
This patch fixes the following testability issues identified by the dynamic
module test.
Global variables defined in function scope cannot be referenced outside
the function, making it impossible to check the return value of these
functions.
Tracked-On: #861
Signed-off-by: Chen, Jinshi <jinshi.chen@intel.com>
After rebooting guest, CPPC initialization failed because _CST and _CPC
missed in DSDT table. When writing _CST and _CPC in DSDT table, it gets
cx_cnt or px_cnt as condition. Getting cx_cnt or px_cnt triggers
the hypercall hcall_get_cpu_pm_state. The hypercall hcall_get_cpu_pm_state
uses VM_CREATED as VM state's condition. While, after rebooting guest,
the VM state is VM_PAUSED when writing _CST and _CPC in DSDT table.
Therefore, changing VM state's condition from VM_CREATED to VM_CREATED or
VM_PAUSED for hcall_get_cpu_pm_state can solve the CPPC initialization
failed issue after rebooting guest.
Tracked-On: #8695
Signed-off-by: Yuan Lu <yuan.y.lu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Fix below compilation error when building the module test for multiboot_priv.h.
./boot/multiboot/multiboot_priv.h: In function ‘boot_from_multiboot’:
./boot/multiboot/multiboot_priv.h:33:27: error: ‘MULTIBOOT_INFO_MAGIC’ undeclared (first use in this function)
33 | return ((magic == MULTIBOOT_INFO_MAGIC) && (info != 0U));
Tracked-On: #861
Signed-off-by: Gao, Shiqing <shiqing.gao@intel.com>
Guest VM, such as Linux, may read RESET_CONTROL(0xCF9) register
before writing to, in this case, ACRN should not always return
dummy value.
Tracked-On: #8688
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Determine the size of drhd_dev_scope based on DRHD_MAX_DEVSCOPE_COUNT
in board file instead of hardcoding. The current default value 16 will
be used if it is not defined in board file to keep compatibility, a
warning will be raised in this case.
Tracked-On: #8494
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
GAI Tooling Notice: These contents may have been developed with support from one
or more generative artificial intelligence solutions.
ACRN hypervisor is decomposed into a series of components and modules. The
module design in hypervisor is to add inline doxygen style comments above
functions, macros, structures, etc.
This patch is to add comments for some elements in hwmgmt_page module.
Tracked-On: #8665
Signed-off-by: Haiwei Li <haiwei.li@intel.com>
GUEST_FLAG_STATELESS indicates guest is running a stateless operating
system and need to be shutdown forcefully without data loss. This flag
is only appalicable to pre-launched VM. For TEE_VM, this flag will be
set implicitly.
Tracked-On: #8671
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Now multiboot modules memory is already reserved from e820 in function
`alloc_mods_memory()` and Service VM will not corrupt pre-launched VM
modules.
So remove the code of Service VM delayed loading.
Tracked-On: #8652
Signed-off-by: Haiwei Li <haiwei.li@intel.com>
The definition of elf32_prog_entry with wrong comments,
p_filesz should means size of segment in file and p_memsz
should means size of segment in memory.
Tracked-On: #8642
Signed-off-by: Zhang Chen <chen.zhang@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
The elf images can't be loaded correctly because
the elf_loader copy_to_gpa with wrong size.
The p_filesz and p_memsz both belong to elf32_prog_entry,
this data structure describes segments loaded in ram.
p_filesz means size of segment in file and p_memsz
means size of segment in memory.
ELF loader should copy elf_img to gpa with the
size of p_prg_tbl_head32->p_filesz.
Tracked-On: #8642
Signed-off-by: Zhang Chen <chen.zhang@intel.com>
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
This patch enable guest multiboot support. Try to find
the multiboot header in normal elf guest image.
Introduce the multiboot related basic functions to
initialize multiboot structure. Including
prepare_multiboot_mmap, prepare_loader_name and
find_img_multiboot_header.
Tracked-On: #8642
Signed-off-by: Victor Sun <victor.sun@intel.com>
Signed-off-by: Zhang Chen <chen.zhang@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
For the TEE and android kernelflinger boot requirements,
elf_loader need to support the multiboot protocol.
This patch define a memory block to store ELF format VM load
params in guest address space. At the same time, prepare the elf
cmdline field and memory map for the guest kernel.
Tracked-On: #8642
Signed-off-by: Victor Sun <victor.sun@intel.com>
Signed-off-by: Zhang Chen <chen.zhang@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
Except Linux guest, elf guest also need support bootargs.
Currently VM bootargs support all type of guest.
Tracked-On: #8642
Signed-off-by: Zhang Chen <chen.zhang@intel.com>
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
This patch is to allow user to pin vUART timer to specific pCPU via ACRN
config tool. User can configure by setting "vUART timer pCPU ID" under
Hypervisor->Advanced Parameters.
Tracked-On: #8648
Signed-off-by: Haiwei Li <haiwei.li@intel.com>
Introduce an interface to define Tx/Tx buffer size via ACRN config tool.
User can configure under Hypervisor->Advanced Parameters.
Tracked-On: #8644
Signed-off-by: Haiwei Li <haiwei.li@intel.com>
rtc_halted() is not invoked anywhere in the code.
This patch removes this unused function to fix below error.
error: unused function 'rtc_halted' [-Werror,-Wunused-function]
Tracked-On: #861
Signed-off-by: Gao, Shiqing <shiqing.gao@intel.com>
This patch fixes the following error:
error: variable 'sid' is used uninitialized whenever 'if' condition is true
[-Werror,-Wsometimes-uninitialized]
Tracked-On: #861
Signed-off-by: Gao, Shiqing <shiqing.gao@intel.com>
