We will use timerfd and epoll mechanism to emulate kinds of timers like
PIT/RTC/WDT/PMTIMER/... in device model under Linux. The api is unified
in this patch.
Compare with sigevent mechanism, timerfd has a advantage that it could
avoid race condition on resource accessing in the async sigev thread.
change log:
v1 -> v2: add NULL pointer check for function parameter;
v2 -> v3: rename file name of vtimer.* to timer.*;
rename structure name of vtimer to acrn_timer;
add read() in timer handler to consume I/O event;
v3 -> v4: replace bool clock_realtime with int clockid;
close acrn_timer->fd properly;
Tracked-On: #1489
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
ABL pass seed_lists to HV through different interface/structures.
So, in this patch, add interface to retrieve seed from ABL and refactor
the seed parsing logic.
Tracked-On: #1488
Signed-off-by: Qi Yadong <yadong.qi@intel.com>
Acked-by: Zhu Bing <bing.zhu@intel.com>
@vioapic_set_pinstate() & vioapic_need_intr(),
add checking input value range for 'pin'.
Tracked-On: #1479
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
According to SDM 6.5 exception classification, if the fault
happens, the CPU will return to the faulting instruction. So
we shouldn't change rip to the next instruction if inject fault
to guest.
Tracked-On: #1473
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
All the platforms supported by ACRN supports x2APIC. So enabled
x2APIC for ACRN hv. Removed any code that is needed for xAPIC mode
of operation.
Tracked-On: #1455
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Reviewed by: Yonghua Huang <yonghua.huang@intel.com>
Let OBJS target depend on VERSION file instead of other targets like
install/all depending on it, since the version.h is being included in
.c files.
This fixes a following compilation issue:
| In file included from include/hv_debug.h:10,
| from include/hypervisor.h:37,
| from arch/x86/cpu.c:7:
| arch/x86/cpu.c: In function 'bsp_boot_post':
| arch/x86/cpu.c:453:4: error: 'HV_FULL_VERSION' undeclared...
Tracked-On: #1441
Signed-off-by: Ming Liu <liu.ming50@gmail.com>
Return value should be checked,fix it by add
"void" when the function return value is not used.
V1->V2:
replace printf with pr_warn.
V2->V3:
change the commit to make read easily.
Tracked-On:#861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This reverts partial of commit: 9bf5aafe "script: workarounds for UOS of
4.19-rc kernel", since our fixing patch for kernel crash when audio passthru
is ready.
Tracked-On:#1461
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
mngr_send_msg() could take mngr descriptor or real socket fd as argument based on
an assuption that real socket fd is less than 1024, which may be an issue.
This commit takes the real socket fd as descriptor, to avoid the conversion between them.
Tracked-On: #1477
Signed-off-by: Tao, Yuhong <yuhong.tao@intel.com>
Signed-off-by: Yan, Like <like.yan@intel.com>
This patch resolves acrn-dm crash issue when acrnd boots up the acrn-dm.
The rootcause is mevent_enable and mevent_disable have NULL pointer as
its parameter if uart backend is not tty capable, so add check code for
the uart backend before invoking mevent_enable and mevent_disable.
The issue can be reproduced when acrnd boots up the acrn-dm.
Tracked-On: #1466
Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Reviewed-by: Tomas Winkler <tomas.winkler@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
MISRA-C required the suffix(U/UL), such as:
(1) ---> (1U)
(1) ---> (1UL)
(1U << 0) ---> (1U << 0U)
This patch will add the suffix(U/UL) to come up MISRA-C into
hypervisor/include directory.
Tracked-On: #1468
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
For acrn-dm cmd options, there are some mismatch usage from acrn-dm help
message.
This patch will cleanup them.
Tracked-On: #1469
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Reviewed-by: Jason Chen <jason.cj.chen@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
VirtIO v1.0 spec 04 5.2.5:
- Protocol unit size is always 512 bytes.
- blk_size (logical block size) and physical_block_exp (physical block
size) do not affect the units in the protocol, only performance.
VirtIO v1.0 spec 04 5.2.6.1:
- A driver MUST NOT submit a request which would cause a read or write
beyond capacity.
Reject the requests that violate these terms.
v1 -> v2:
- add more comments for clarity
Tracked-On: #1422
Signed-off-by: Peter Fang <peter.fang@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
There is no GEOM framework in Linux. Remove dead code.
v1 -> v2:
- complete removal of the entire GEOM logic
Tracked-On: #1422
Signed-off-by: Peter Fang <peter.fang@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
An issue reported on KBL NUC (No APIC-V), when runing GVT test
case, it is easily to cause SOS/UOS hung. This patch is to root
cause it and how to avoid it.
On some platforms with no APIC-V support, this modidication can
avoid SOS hung when no IRR but event pending bit set.
If no APIC-V, interrupt injection will use IRR in vLAPIC and
event pending bitmap; work logic as following (set ABC for notes):
1. in ISR or when UOS send an interrupt to SOS/VHM (like IO request),
step A: set IRR --> step B: set event pending bit;
2. in SOS event handing, step C: check/clear event pending bit -->
step D: probe/get IRR --> step E: clear/handle IRR.
3. after that, it will probe IRR again to check if other IRR left:
step F: probe IRR --> step G: set event pending bit --> step H:
enable IRQ window in VMX.
Before, from step C to D, if pending bit checked, but no IRR, it will
return -1, then the CPU will goto ZOMBIE status. It can cause
SOS hung. It can happen occasionally under following case :
4. between UOS step A and step B, SOS can goto step F, so it
gets IRR, and step G --> step H, then SOS enter non-root mode, for
IRQ window enabled, it will cause vmexit to continue step C/D/E.
5. then UOS does step B, to set pending bit, but no IRR now. When next
vmexit, SOS does step C and D, it can't get IRR, failure happens.
In summary, a failed case steps: A-->F-->G-->H-->C-->D-->E-->B-->C-->D
So we allow that when event pending bit checked, IRR could be cleared
already.It just wastes one probe time occasionally.
Tracked-On: #1363
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
to enable APICv Posted interrupt supported, following the
specifications defined in Intel SDM Section #29.6, Volume3.
Posted-interrupt processing is a feature by which a processor
processes the virtual interrupts by recording them as pending
on the virtual-APIC page.
Injecting interrupts to VCPU from remote CPU without causing
VM exit on the destination, following steps in SDM Section 29.6,volume3:
Tracked-On: #1447
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
use pin_state[pin] to record vpic pin signal, and change the interface name
accordingly.
Tracked-On: #1269
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
NHLT table contains the settings some audio drivers need.
An ACPI method is used to get NHLT table address & length.
In current DM code, the NHLT talbe length in the ACPI method
is hardcoded, which will cause troubles when the length of the
table changed.
This patch replaces the hardcoded NHLT table length according to
the table length read from SOS.
Tracked-On: #1461
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
Now we have name reuse definitions in hypervisor as following:
"enum cpu_state cpu_state" in per_cpu.h,
"struct shell_cmd *shell_cmd" in shell_priv.h.
MISRAC requires that tag names shall not be reused anywhere
with in a program.So these definitions violate MISRAC rules
"identifier resue".This patch is used to fix it.
1. modify the definitions to "enum pcpu_boot_state boot_state"
and "struct shell_cmd *cmds".
2. modifty the relevant usage.
v1->v2
update commit message to be more explicit.
v2->v3
update the enum definition.
Tracked-On: #861
Signed-off-by: Junjun Shan <junjun.shan@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Now, UOS will use hypercall to init BSP state, we could remove
set_bsp_real_mode_entry() and set_bsp_protect_mode_regs().
For SOS, GDT will inherit from SBL or UEFI. For UOS, DM will
prepare GDT. We don't need hypervisor to prepare GDT for guest.
The entry_addr of vcpu struct could be removed. The guest entry
is set through BSP rip register.
GUEST_CFG_OFFSET is not needed any more after this patchset.
Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Move vcpu mode set to function vcpu_set_regs.
Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
For UOS, we need to call hypercall to set BSP init state now.
So we can't combint the vm start and vm reset (vm reset will
reset the vcpu context). Remove vm start from reset_vm. DM
needs to start vm after every vm reset.
Update DM to set UOS BSP init state after vm reset and before
vm start.
Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
For UOS, there is no BSP init state saved in hv. We always need
DM to set BSP init state by using hypercall. So we can't auto
start vm during vm reset.
Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Now, we make UOS to set BSP init state by using hypercall. We
could drop the old UOS loader in HV and make vm loader in HV
only for SOS.
Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
to use new interface to set the state of guest BSP (entries, general
registers etc) when DM load bzimage.
Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
to use new interface to set the state of guest BSP (entries, general
registers etc) when DM load vsbl.
Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Add ioctl parameter and API to set vcpu regs. The guest software
loader will call this API to set guest vcpu registers.
Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
DM will use this hypercall to initialize the UOS BSP state.
Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Use customized function to generate proper config.h
which depend on kconfig,write the customized format
to support it.
V1->V2:
Add comments.
Tracked-On: #861
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
Add new format to parsed by kconfig to support
U and UL.
When config is 'int',if this symbol have 'range'
key words and bigger or qeual to 0,the int macro
will have suffix 'U'.
When config is 'hex',the suffix is 'U'.
When config have 'help' keywords,and the help contents
have the string "64-bit integer",it will add suffix 'L'.
V1->V2:
1.modified the comments to let it much eaisy to understand.
2.change the values' name protected_foot,protected_tai to
guard_begin and guard_end.
3.add regex to identified the '64-bit' and 'integer'.
V2->V3:
1.remove kconfiglib internal attribute
2.use config_string to avoid no active config entry
Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Use genld.sh instead of config.h to generate link_ram.ld.
It can avoid the conflicts of the syntax between ld script and
C.
V1->V2:
change the deps name to config,
Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
reviewed-by: Junjie Mao <junjie.mao@intel.com>
The write_dsdt_xhci function is use for describe the xdci dsdt table.
Correct its name.
Tracked-On: #1444
Signed-off-by: Yu Wang <yu1.wang@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
From SDM Vol3 26.3.2.5:
Once the virtual interrupt is recognized, it will be delivered in VMX
non-root operation immediately after VM entry(including any specified
event injection) completes.
So the hardware can handle vmcs event injection and evaluation/delivery
of apicv virtual interrupts in one time vm-entry.
This patch move the apicv irr/rvi sync before handle vmcs events
injection. The old code cause the apicv virtual interrupt evaluation and
delivery be handled until next vm-exit if met pending exceptions.
Tracked-On: #1443
Signed-off-by: Yu Wang <yu1.wang@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
The vcpu state is initialized outside of init_guest_state:
- SOS BSP state is initialized in SOS loader
- UOS BSP state is initialized in UOS loader
- AP state is initialized during SIPI signal emulation
We could make init_guest_state only update the vcpu state
to VMCS structure.
Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
NOTE: this patch is only workaround patch for UOS BSP state init.
Eventually, the DM will call hypercall to init UOS BSP state.
We use this workaround patch here to simplify the init_guest_state.
Will make the caller of init_guest_state calls init_guest_vmx
directly.
Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
We move the SOS BSP state init to vm loader and drop
function init_guest_context_vm0_bsp.
Update the definition of vm0_boot_context to fix code
violations.
Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
With reset_vcpu_regs as pre-condition, we only need to set
cs_selector and cs_base for AP.
We call set_ap_entry in two places:
1. When emulation AP SIPI
2. When sos BSP resume from S3. The BSP is resumed to real
mode with entry set to wakeup_vec. We call set_ap_entry
API here with entry twisted from wakeup_vec.
Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
This reset_vcpu_regs function will reset the vcpu registers to
default value: realmode with entry 0xFFFFFFF0
Make call to reset_vcpu_regs during create_vcpu and reset_vcpu
Tracked-On: #1231
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
movb is used for registers STATUS and CFGGENERATION whose size is 1
byte. Previously hv cannot report the correct MMIO trap size for
movb and virtio hard coded their size to 4 as a workaround. hv fixed
movb instruction emulation and MMIO size can be reported correctly.
This patch removes those workaround.
commit 9df8790ffc ("hv: Fix two minor issues in instruction emulation code")
Tracked-On: #1449
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
If defined CONFIG_VM0_DESC, HV will use predefined vm0_desc
to config VM0,now it is unneccessary, then remove these code.
Tracked-On: #861
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Add a function to do msix table deinit.
1. call api to reset msix entry in hypervisor
2. free virtual msix table memory
3. unmap pba page if any
4. unmap the pages passhtru to uos in MSIX BAR if any
Tracked-On: #1222
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
Normally, for devices support MSI-X, PBA is passed-through to guest.
However, PBA and MSI-X table share the same bar, and part of PBA and
MSI-X table may share a same page for some devices.
If that is the case, the part of PBA within the page should be emulated
rather than passed-through.
This patch adds PBA emulation support for MSI-X.
Tracked-On: #1222
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Yin Fengwei <fengwei.yin@intel.com>
This reverts partial of commit: 9bf5aafe "script: workarounds for UOS of
4.19-rc kernel", since our fixing patch for the PVMMIO ppgtt update bug
is ready.
For the remaining audio pass-through workaround, we still need to keep
it until it's fixed.
Tracked-On: #1413
Signed-off-by: Min He <min.he@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
TR selector initianlization using pre-defined HOST_GDT_RING0_CPU_TSS_SEL
rather than loading from register. Instead calculating real base address
of TSS based on TR selector and gdt, getting it from per cpu data.
Tracked-On: #1394
Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
