Commit Graph

118 Commits

Author SHA1 Message Date
Victor Sun
b6684f5b61 HV: sanitize config file for whl-ipc-i5
- remove limit of CONFIG_HV_RAM_SIZE which is for scenario of 2 VMs only,
the default size from Kconfig could build scenario which up to 5 VMs;

- rename whl-ipc-i5_acpi_info.h to platform_acpi_info.h, since the former
one should be generated by acrn-config tool;

- add SOS related macros in misc.h, otherwise build scenarios which has
SOS VM would be failed;

Tracked-On: #4463

Signed-off-by: Victor Sun <victor.sun@intel.com>
2020-03-06 08:34:12 +08:00
Vijay Dhanraj
b6c0558b60 HV: Update existing board.c files for RDT MBA
This patch updates board.c files for RDT MBA on existing
platforms. Also, fixes setting RDT flag in  WHL config file.

Tracked-On: #3725
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-03-04 17:33:50 +08:00
Yuan Liu
320ed6c238 hv: refine init_one_dev_config
The init_one_dev_config is used to initialize a acrn_vm_pci_dev_config
SRIOV needs a explicit acrn_vm_pci_dev_config to create a VF vdev,so
refine it to return acrn_vm_pci_dev_config.

Tracked-On: #4433

Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-03-03 09:32:11 +08:00
Yuan Liu
5e989f13c6 hv: check if there is enough room for all SRIOV VFs.
Make the SRIOV-Capable device invisible from SOS if there is
no room for its all virtual functions.

v2: fix a issue that if a PF has been dropped, the subsequent PF
    will be dropped too even there is room for its VFs.

Tracked-On: #4433

Signed-off-by: Yuan Liu <yuan1.liu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-02-28 14:04:01 +08:00
Vijay Dhanraj
cef3322da8 HV: Add WhiskeyLake board configuration files
This patch adds offline tool generated WhiskeyLake
board configurations files.

Tracked-On: #3715
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-02-27 10:44:07 +08:00
Vijay Dhanraj
eaad91fd71 HV: Remove RDT code if CONFIG_RDT_ENABLED flag
is not set

This patch does the following,
1. Removes RDT code if CONFIG_RDT_ENABLED flag is
not set.
2. Set the CONFIG_RDT_ENABLED flag only on platforms
that support RDT so that build scripts will automatically
reflect the config.

Tracked-On: #3715
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-02-27 10:44:07 +08:00
Vijay Dhanraj
887e3813bc HV: Add both HW and SW checks for RDT support
There can be times when user unknowinlgy enables
CONFIG_CAT_ENBALED SW flag, but the hardware might
not support L3 or L2 CAT. In such case software can
end up writing to the CAT MSRs which can cause
undefined results. The patch fixes the issue by
enabling CAT only when both HW as well software
via the CONFIG_CAT_ENABLED supports CAT.

The patch also address typo with "clos2prq_msr"
function name. It should be "clos2pqr_msr" instead.
PQR stands for platform qos register.

Tracked-On: #3715
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-02-27 10:44:07 +08:00
Vijay Dhanraj
b8a021d658 HV: split L2 and L3 cache resource MSR
Upcoming intel platforms can support both L2 and L3
but our current code only supports either L2 or L3 CAT.
So split the MSRs so that we can support allocation
for both L2 and L3.

This patch does the following,
1. splits programming of L2 and L3 cache resource
based on the resource ID.
2. Replace generic platform_clos_array struct with resource
specific struct in all the existing board.c files.

Tracked-On: #3715
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-02-27 10:44:07 +08:00
Vijay Dhanraj
2597429903 HV: Rename cat.c/.h files to rdt.c/.h
As part of rdt cat refactoring, goal is to combine all rdt
specific features such as CAT under one module. So renaming
rdt resouce specific files such as cat.c/.h to generic rdt.c/.h
files.

Tracked-On: #3715
Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2020-02-27 10:44:07 +08:00
Wei Liu
f3a4b2325f hv: add P2SB device to whitelist for apl-mrb
apl-mrb need to access P2SB device, so add 00:0d.0 P2SB device to
whitelist for platform pci hidden device.

Tracked-On: #3475
Signed-off-by: Wei Liu <weix.w.liu@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Victor Sun <victor.sun@intel.com>
2020-02-24 12:21:29 +08:00
Zide Chen
cc6f094926 hv: CAT is supposed to be enabled in the system level
In platforms that support CAT, when it is enabled by ACRN, i.e.
IA32_resourceType_MASK_n registers are programmed with customized values,
it has impacts to the whole system.

The per guest flag GUEST_FLAG_CLOS_REQUIRED suggests that CAT may be
enabled in some guests, but not in others who don't have this flag,
which is conceptually incorrect.

This patch removes GUEST_FLAG_CLOS_REQUIRED, and adds a new Kconfig
entry CAT_ENABLED for CAT enabling. When it's enabled, platform_clos_array[]
defines a set of system-wide Class of Service (COS, or CLOS), and the
per guest vm_configs[].clos associates the guest with particular CLOS.

Tracked-On: #2462
Signed-off-by: Zide Chen <zide.chen@intel.com>
2020-02-17 08:51:59 +08:00
Li Fei1
65f3751ea3 hv: pci: add hide pci devices configuration for apl-up2
Other Platforms are not added for now.

Tracked-On: #3465
Signed-off-by: Li Fei1 <fei1.li@intel.com>
2020-01-07 16:05:30 +08:00
Zide Chen
742abaf2e6 hv: add sanity check for vuart configuration
- target vm_id of vuart can't be un-defined VM, nor the VM itself.
- fix potential NULL pointer dereference in find_active_target_vuart()

Tracked-On: #3854
Signed-off-by: Zide Chen <zide.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-12-30 09:24:59 +08:00
Yin Fengwei
e5117bf19a vm: add severity for vm_config
Add severity definitions for different scenarios. The static
guest severity is defined according to guest configurations.

Also add sanity check to make sure the severity for all guests
are correct.

Tracked-On: #4270
Signed-off-by: Yin Fengwei <fengwei.yin@intel.com>
2019-12-23 15:15:09 +08:00
Victor Sun
ea3476d22d HV: rename CONFIG_MAX_PCPU_NUM to MAX_PCPU_NUM
rename the macro since MAX_PCPU_NUM could be parsed from board file and
it is not a configurable item anymore.

Tracked-On: #4230

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-12-12 13:49:28 +08:00
Victor Sun
15da33d8af HV: parse default pci mmcfg base
The default PCI mmcfg base is stored in ACPI MCFG table, when
CONFIG_ACPI_PARSE_ENABLED is set, acpi_fixup() function will
parse and fix up the platform mmcfg base in ACRN boot stage;
when it is not set, platform mmcfg base will be initialized to
DEFAULT_PCI_MMCFG_BASE which generated by acrn-config tool;

Please note we will not support platform which has multiple PCI
segment groups.

Tracked-On: #4157

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-12-02 16:20:24 +08:00
Victor Sun
3411f00b5b HV: fix misra violation on platform clos array
MISRA C requires specified bounds for arrays declaration, previous declaration
of platform_clos_array in board.h does not meet the requirement.

Tracked-On: #3987

Signed-off-by: Victor Sun <victor.sun@intel.com>
2019-11-08 16:40:14 +08:00
Victor Sun
c77d275e9d HV: clean up DMAR MACROs for sample platform acpi info
Remove redundant DMAR MACROs for given platform_acpi_info files because
CONFIG_ACPI_PARSE_ENABLED is enabled for all boards by default. The DMAR
info for nuc7i7dnb is kept as reference in the case that ACPI_PARSE_ENABLED
is not set in Kconfig.

As DMAR info is not provided for apl-mrb, the platform_acpi_info.h under
apl-mrb config folder is meaningless, so also remove this file and let
hypervisor parse ACPI for apl-mrb;

Tracked-On: #3977

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-11-08 16:40:14 +08:00
Victor Sun
9e92f3cdf5 HV: move dmar info definition to board.c
The DMAR info is board specific so move the structure definition to board.c.
As a configruation file, the whole board.c could be generated by acrn-config
tool for each board.

Please note we only provide DMAR info MACROs for nuc7i7dnb board. For other
boards, ACPI_PARSE_ENABLED must be set to y in Kconfig to let hypervisor parse
DMAR info, or use acrn-config tool to generate DMAR info MACROs if user won't
enable ACPI parse code for FuSa consideration.

The patch also moves the function of get_dmar_info() to vtd.c, so dmar_info.c
could be removed.

Tracked-On: #3977

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-11-08 16:40:14 +08:00
Victor Sun
589be88cf6 HV: link CONFIG_MAX_IOMMU_NUM and MAX_DRHDS to DRHD_COUNT
The value of CONFIG_MAX_IOMMU and MAX_DRHDS are identical to DRHD_COUNT
which defined in platform ACPI table, so remove CONFIG_MAX_IOMMU_NUM
from Kconfig and link these three MACROs together.

Tracked-On: #3977

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-11-08 16:40:14 +08:00
Shiqing Gao
c8bcab9006 hv: pci: update function "bdf_is_equal"
- update the function argument type to union
  Declaring argument as pointer is not necessary since it
  only does the comparison.

Tracked-On: #1842
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
2019-09-25 13:45:39 +08:00
Shuo A Liu
1c526e6d16 hv: use vcpu_affinity[] in vm_config to support vcpu assignment
Add this vcpu_affinity[] for each VM to indicate the assignment policy.
With it, pcpu_bitmap is not needed, so remove it from vm_config.
Instead, vcpu_affinity is a must for each VM.

This patch also add some sanitize check of vcpu_affinity[]. Here are
some rules:
  1) only one bit can be set for each vcpu_affinity of vcpu.
  2) two vcpus in same VM cannot be set with same vcpu_affinity.
  3) vcpu_affinity cannot be set to the pcpu which used by pre-launched VM.

v4: config SDC with CONFIG_MAX_KATA_VM_NUM
v5: config SDC with CONFIG_MAX_PCPU_NUM

Tracked-On: #3663
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Signed-off-by: Yu Wang <yu1.wang@intel.com>
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
2019-09-24 11:58:45 +08:00
Shuo A Liu
ca2540fe8c hv: return pre-defined vcpu_num from HV to upper layer
There is plan that define each VM configuration statically in HV and let
DM just do VM creating and destroying. So DM need get vcpu_num
information when VM creating.

This patch return the vcpu_num via the API param. And also initial the
VMs' cpu_num for existing scenarios.

Tracked-On: #3663
Signed-off-by: Jason Chen CJ <jason.cj.chen@intel.com>
Signed-off-by: Yu Wang <yu1.wang@intel.com>
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-09-24 11:58:45 +08:00
Shuo A Liu
59e39c5fbb hv: move MAX_PCPU_NUM from Kconfig to header file
MAX_PCPU_NUM is different on various BOARDs. So we move the generic
definition from Kconfig to each board's config header file.

Tracked-On: #3663
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
2019-09-24 11:58:45 +08:00
Victor Sun
398137990e HV: add memmap param for hvlog in sos cmdline
Reserve memory for hv sbuf to avoid its possible overwriting on kernel memory.

For apl-up2, move hv_log address to 0x5de00000 to avoid possible conflict with
HV_RAM which start from 0x5e000000;

For nuc6cayh, move HV_RAM_START to 0x20000000 to avoid possible conflict with
hv_log which start from 0x1fe00000;

Tracked-On: #3533

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
2019-09-17 09:12:03 +08:00
Victor Sun
d188afbc59 HV: add acpi info header for nuc7i7dnb
Currently nuc7i7dnb board is using default platform acpi info file so causes
S3/S5 not working properly.

This patch updates the correct ACPI info for nuc7i7dnb board.

Tracked-On: #3609

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Yin Fengwei <fengwei.yin@intel.com>
2019-09-11 14:00:53 +08:00
dongshen
295701cc55 hv: remove mptable code for pre-launched VMs
Now that ACPI is enabled for pre-launched VMs, we can remove all mptable code.

Tracked-On: #3601
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-08-29 10:12:25 +08:00
dongshen
b447ce3d86 hv: add ACPI support for pre-launched VMs
Statically define the per vm RSDP/XSDT/MADT ACPI template tables in vacpi.c,
RSDP/XSDT tables are copied to guest physical memory after checksum is
calculated. For MADT table, first fix up process id/lapic id in its lapic
subtable, then the MADT table's checksum is calculated before it is copies to
guest physical memory.

Add 8-bit checksum function in util.h

Tracked-On: #3601
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-08-29 10:12:25 +08:00
Victor Sun
2736b6c4cd HV: add vCOM2 setting for hybrid and industry scenario
The vCOM2 of each VM is designed for VM communication, one VM could send
command or request to another VM through this channel. The feature will
be used for system S3/S5 implementation.

On Hybird scenario, vCOM2 of pre-launched VM will connect to vCOM2 of SOS_VM;
On Industry scenario, vCOM2 of post-launched RTVM will connect to vCOM2 of
SOS_VM.

Tracked-On: #3602

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-08-22 13:12:54 +08:00
Victor Sun
c8cdc7e807 HV: move vCOM setting from Kconfig to board configs
The settings of SOS VM COM1 which is used for console is board specific,
and this result in SOS VM COM2 which used for VM communication is also
board specific, so move the configure method from Kconfig to board configs
folder. The MACRO definition will be handled by acrn-config tool in future.

Tracked-On: #3602

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@intel.com>
2019-08-22 13:12:54 +08:00
Victor Sun
5a1842afb8 HV: set sos root dev of apl-up2 to mmcblk0p3
Set sos root device of apl-up2 to mmcblk0p3 and let UP2 uefi variant
and sbl variant share one config for now.

Tracked-On: #3214

Signed-off-by: Victor Sun <victor.sun@intel.com>
2019-08-22 09:10:38 +08:00
Victor Sun
6c99f76404 HV: prepare ve820 for apl up2
We need ve820 table to enable prelaunched VM for apl-up2 board;

Tracked-On: #3214

Signed-off-by: Victor Sun <victor.sun@intel.com>
2019-08-22 09:10:38 +08:00
huihuang.shi
f147c388a5 hv: fix Violations touched ACRN Coding Guidelines
fix violations touched below:
1.Cast operation on a constant value
2.signed/unsigned implicity conversion
3.return value unused.

V1->V2:
1.bitmap api will return boolean type, not need to check "!= 0", deleted.
2.The behaves ~(uint32_t)X and (uint32_t)~X are not defined in ACRN hypervisor Coding Guidelines,
removed the change of it.
Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
2019-08-15 09:47:11 +08:00
Li, Fei1
d82a00a128 hv: vpci: remove pBDF configure for emulated device
Since now we use vBDF to search the device for PCI vdev.

Tracked-On: #3475
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-08-12 10:00:44 +08:00
Li, Fei1
4c8e60f1d0 hv: vpci: add each vdev_ops for each emulated PCI device
Add a field (vdev_ops) in struct acrn_vm_pci_dev_config to configure a PCI CFG
operation for an emulated PCI device. Use pci_pt_dev_ops for PCI_DEV_TYPE_PTDEV
by default if there's no such configure.

Tracked-On: #3475
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-08-09 14:19:49 +08:00
Li, Fei1
ff54fa2325 hv: vpci: add emulated PCI device configure for SOS
Add emulated PCI device configure for SOS to prepare for add support for customizing
special pci operations for each emulated PCI device.

Tracked-On: #3475
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-08-09 14:19:49 +08:00
Li, Fei1
eb21f205e4 hv: vm_config: build pci device configure for SOS
Align SOS pci device configure with pre-launched VM and filter pre-launched VM's
PCI PT device from SOS pci device configure.

Tracked-On: #3475
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2019-08-06 11:51:02 +08:00
Victor Sun
9139f94ec9 HV: correct CONFIG_BOARD string of apl up2
The CONFIG_BOARD value in defconfig should match with Makefile, otherwise
the build might be failed in some condition.

Tracked-On: #2291

Signed-off-by: Victor Sun <victor.sun@intel.com>
2019-07-30 09:50:10 +08:00
Victor Sun
555a03db99 HV: add board specific cpu state table to support Px Cx
Currently the Px Cx supported SoCs which listed in cpu_state_tbl.c is limited,
and it is not a wise option to build a huge state table data base to support
Px/Cx for other SoCs. This patch give a alternative solution that build a board
specific cpu state table in board.c which could be auto-generated by offline
tool, then the CPU Px/Cx of customer board could be enabled;

Hypervisor will search the cpu state table in cpu_state_tbl[] first, if not
found then go check board_cpu_state_tbl. If no matched cpu state table is found
then Px/Cx will not be supported;

Tracked-On: #3477

Signed-off-by: Victor Sun <victor.sun@intel.com>
2019-07-29 20:25:16 +08:00
Victor Sun
3cf1daa480 HV: move vbar info to board specific pci_devices.h
The vbar info which hard-coded in scenarios/logical_partition/pt_dev.c
is board specific actually, so move these information to
arch/x86/configs/$(CONFIG_BOARD)/pci_devices.h.

Please be aware that the memory range of vBAR should exactly match with
the e820 layout of VM.

Tracked-On: #3214

Signed-off-by: Victor Sun <victor.sun@intel.com>
2019-07-23 09:12:50 +08:00
Victor Sun
a27ce27a2e HV: rename nuc7i7bnh to nuc7i7dnb
NUC7i7BNH is not a board name but a product name of KBL NUC, and it is
outdated to support LOGICAL_PARTITION scenario and HYBRID scenario.

NUC7i7DNH is the product name of KBL NUC that ACRN currently supported,
but its official board name is NUC7i7DNB, so change the folder name from
"nuc7i7bnh" to "nuc7i7dnb" under arch/x86/configs/.

Please refer more details on below documentation:
Intel® NUC Board/Kit NUC7i7DN Technical Product Specification

Tracked-On: #3446

Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Xiangyang Wu <xiangyang.wu@linux.intel.com>
2019-07-22 16:21:12 +08:00
Victor Sun
1884bb0551 HV: modify HV RAM and serial config for apl-nuc
- To support grub multiboot for nuc6cayh, we should put hv ram start
  at a suitable address;

- Enable HSUART controller at PCI 0:18.0 as HV serail port;

Tracked-On: #3214

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-07-11 14:48:26 +08:00
Victor Sun
f18dfcf522 HV: prepare ve820 for apl nuc
Add ve820 table for apl nuc board to enable prelaunched VM on it;

Tracked-On: #3214

Signed-off-by: Victor Sun <victor.sun@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-07-11 14:48:26 +08:00
Huihuang Shi
79d033027b HV: fix vmptable "Casting operation to a pointer"
ACRN Coding guidelines requires two different types pointer can't
convert to each other, except void *.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
2019-07-11 13:57:21 +08:00
Huihuang Shi
9063504bc8 HV: ve820 fix "Casting operation to a pointer"
ACRN Coding guidelines requires two different types pointer can't
convert to each other, except void *.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
2019-07-11 13:57:21 +08:00
Huihuang Shi
714162fb8b HV: fix violations touched type conversion
ACRN Coding guidelines requires type conversion shall be explicity.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-07-11 09:16:09 +08:00
Huihuang Shi
4b6dc0255f HV: fix vmptable misc violations
Fix the violations list below:
1.Function should have one return entry.
2.Do not use -- or ++ operation.
3.For loop should be simple, shall not use comma operations.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-07-09 10:36:44 +08:00
Huihuang Shi
3a61530d4e HV:fix simple violations
Fix the violations not touched the logical.
1.Function return value not checked.
2.Logical conjuctions need brackets.
3.No brackets to then/else.
4.Type conversion without cast.

Tracked-On: #861
Signed-off-by: Huihuang Shi <huihuang.shi@intel.com>
2019-06-25 20:09:21 +08:00
Mingqiang Chi
8338cd463b hv: move 3 files to lib & arch folder
move stack_protector.c/retpoline-thunk.S into lib folder
move vmptable.c into arch/x86/config

Tracked-On: #1842
Signed-off-by: Mingqiang Chi <mingqiang.chi@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>

	modified:   Makefile
	renamed:    arch/x86/retpoline-thunk.S -> arch/x86/lib/retpoline-thunk.S
	renamed:    common/stack_protector.c -> lib/stack_protector.c
	renamed:    dm/vmptable.c -> arch/x86/configs/vmptable.c
2019-06-14 14:22:51 +08:00
Zhao Yakui
c71cf753eb ACRN/HV: Add one new board configuration for ACRN-hypervisor
The memory size and IOMMU number are refined to meet with ICL board requirement.
Otherwise the ACRN hypervisor can't be booted on the new ICL board.
ICL(the abbreviation of Ice Lake) is the next generation platform based on 10nm.
CPU is based on Sunny Cove microarchitecture and GPU is based on gen11.
The new board is named as icl-rvp.

Tracked-On: #3216
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Binbin Wu <binbin.wu@intel.com>
2019-06-10 11:23:18 +08:00