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b8a021d658
Upcoming intel platforms can support both L2 and L3 but our current code only supports either L2 or L3 CAT. So split the MSRs so that we can support allocation for both L2 and L3. This patch does the following, 1. splits programming of L2 and L3 cache resource based on the resource ID. 2. Replace generic platform_clos_array struct with resource specific struct in all the existing board.c files. Tracked-On: #3715 Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com> |
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| .. | ||
| apl-mrb | ||
| apl-up2 | ||
| dnv-cb2 | ||
| generic | ||
| icl-rvp | ||
| nuc6cayh | ||
| nuc7i7dnb | ||
| apl-mrb.config | ||
| apl-nuc | ||
| apl-nuc.config | ||
| apl-up2.config | ||
| dnv-cb2.config | ||
| generic.config | ||
| icl-rvp.config | ||
| kbl-nuc-i7 | ||
| kbl-nuc-i7.config | ||
| nuc6cayh.config | ||
| nuc7i7dnb.config | ||
| pci_dev.c | ||
| platform_acpi_info.h | ||
| vacpi.c | ||
| vm_config.c | ||