_STR is another device identification object defined in ACPI spec that
describes a device. This patch collects this string (when available) into
board XML as well.
Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This patch adds the property `irqs` to the class SmallResourceitemIRQ so
that the list of IRQs encoded in this resource item can be retrieved
easily.
Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This patch adds a parser to the PCI routing tables returned by _PRT objects
of platform devices. The parsed result is a list of PRTMappingPackage
instances, each of which is a named tuple with the following fields:
* address: a dword with higher 16 bits being the function number and
lower 16 bits all 1's.
* pin: a byte representing the mapped pin.
* source: either a DeviceDecl of the device that allocates the interrupt
line, or the byte 0.
* source_index:
- If `source` is a DeviceDecl, this is the index of the interrupt
source within that device.
- If `source` is 0, this is the interrupt line connected to the pin.
Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Local variables can be assigned with formal arguments in AML. As a result
when interpreting a DefReturn node, the interpreter shall unwrap multiple
layers of argument/local variable wrappings until a concrete value is
found. This patch implements this logic.
Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Resource template buffers always end with an end tag. Concatenation of two
resource buffers thus requires that the end tag of the first buffer is
stripped. This patch adds this logic to the interpretation of DefConcatRes
AML nodes.
Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
The warning, info and debug logging levels are intended to be used in the
following way.
* Warnings are used when users are expected to be aware of a certain
failure.
* Info messages are used to track parsing process and major internal
errors for development.
* Debug messages are used to collect verbose debug logs.
To align the current usage of logs to the above guidelines, this patch
adjusts the logging level of the following messages:
* DSDT/SSDT interpretation failures are now warnings, not information
* Failures of parsing deferred AML blocks are now information, not debug
messages
The default log level when running `cli.py` is adjusted to WARNING as well,
as INFO is primarily used for development. A new command line option
`loglevel` is added to adjust the log level per user needs.
v2 -> v3:
* Make address collisions in ACPI namespace as an info rather than a
warning.
Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
A DualNamePath clause is a NamePath that only follows rootchar or
prefixpath. Thus, it is never necessary to check if a dot is necessary for
separating segments before a DualNamePath. This patch removes the code that
conduct that check.
Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
It is seen occasionally that a memory/port BAR of a PCI device is
programmed with the address 0 which is clearly invalid. This patch
gracefully handles this case by printing an error to warn the users that
this device cannot be passed through to any VM.
Tracked-On: #6298
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
According to section 19 of ACPI spec 6.4, the following clauses open name
scopes (in addition to the Scope clauses).
- Function
- Device
- Method
- Power Resource
- Thermal Zone
The current AML parser only opens a scope when parsing DefMethod and
DefDevice, however. This patch fixes the AML parsing by opening a scope on
visiting a DefPowerRes or DefThermalZone clause.
Note: Functions in ASL are equivalent to Methods at AML level.
Tracked-On: #6298
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
The current ConditionallyUnregisterSymbolVisitor has the following two
issues.
1. The visitor will crash when a DefIfElse node is not fully parsed due
to failed deferred expansion.
2. Nested DefIfElse of disabled blocks are still checked and one of its
branch may still take effect.
This patch fixes those issues by checking the predicates of a DefIfElse
block only when conditionally_hidden is False and check existence of
TermList and DefElse clauses.
Tracked-On: #6298
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
When parsing a sequence of clauses, it is not necessary to peek an opcode
from the current stream unless that sequence starts with one. Peeking an
opcode is even an error when the actual clause is empty (e.g. as a
TermList).
This patch makes the SequenceFactory only peeking at the next opcode when
the grammar expects one.
Tracked-On: #6298
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This patch refines the AML parser to improve its readability and
performance in the following ways.
1. A Tree object now has the parts of the corresponding object being
member fields. As an example, a Tree with label `DefMethod` now has
members `NameString`, `MethodFlags` and `TermList`.
2. It is now possible to assign names each part of an object. The grammar
is updated to assign different names to the parts with the same type
in the same object.
3. Invocation to intermediate factories is now skipped. As an example,
when parsing a ByteConst that acts as a ByteIndex, the original
implementation invokes the following factories in sequence:
ByteIndex -> TermArg -> DataObject -> ComputationalData -> ByteConst
The factories TermArg, DataObject and ComputationalData does nothing
but forward the parsing to the next-level factory according to the
opcode of the next object. With this patch, the invocation sequence
becomes:
ByteIndex -> ByteConst
i.e. ByteIndex directly passes to ByteConst which can parse the next
opcode.
Tracked-On: #6298
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
The current ACPI AML parser can generate incorrect AST if a DSDT/SSDT
satisfies the following:
1. The body of a method invokes a NameString that is defined later.
2. Before that method the same NameString is also defined but in an outer
scope and with a different number of parameter.
Since method bodies hardly define any further symbol that is referenced
outside the method itself, this patch forces the parsing of method bodies
to be deferred to the second pass when all symbols have been declared.
Tracked-On: #6298
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
The current implementation of I/O buffers have the following issues.
1. I/O buffers are filled with values on creation. This may be fine for
memory-mapped I/O regions, but could be a problem to port I/O regions
and indexed I/O regions.
2. While not commonly seen, it IS witnessed that some devices only allow
its MMIO registers to be accessed with certain width. Accessing such
registers with a larger width will not be handled by the device,
causing SW to get all 1's rather than the actual values in these
registers.
This patch resolves the issues above as follows:
1. I/O buffers now do not access any register on creation. Instead, the
register is accessed only upon requests.
2. The access width of these registers are followed to ensure that the
registers are accessed properly.
The classes that represents buffers when interpreting AML is also
refactored to abstract the common code that manages fields within
buffers. The class hierarchy now looks like this:
BufferBase: Implement methods that registers, reads or writes fields
Buffer(BufferBase): Implement memory buffer
StreamIOBuffer(BufferBase): Implement I/Os available via /dev files
IndexedIOBuffer(BufferBase): Implement I/Os via index/data registers
Tracked-On: #6298
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
DefDevide is now enountered when interpreting host DSDT/SSDT. This patch
implements the interpretation of the integer division operation.
Tracked-On: #6298
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
The current implementation of the AML interpreter continues interpreting a
method after meeting a DefReturn object, which is incorrect. This patch
fixes this issue by raising a dedicated exception on return and catching
that exception on the caller side.
Tracked-On: #6298
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Currently the HV console does not support PCI UART with 64bit BAR, but in the
case that the BAR is in 64bit and the BAR space is below 4GB (i.e. the high
32bit address of the 64bit BAR is zero), HV should be able to support it.
Tracked-On: #6334
Signed-off-by: Victor Sun <victor.sun@intel.com>
When guest kernel has multiple loading segments like ELF format image, just
define one load address in sw_kernel_info struct is meaningless.
The patch removes kernel_load_addr member in struct sw_kernel_info, the load
address should be parsed in each specified format image processing.
Tracked-On: #6323
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
The previous code did not load bzImage start from protected mode part, result
in the protected mode part un-align with kernel_alignment field and then cause
kernel decompression start from a later aligned address. In this case we had
to enlarge the needed size of bzImage kernel to kernel_init_size plus double
size of kernel_alignment.
With loading issue of bzImage protected mode part fixed, the kernel needed size
is corrected in this patch.
Tracked-On: #6323
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
When LaaG boots with bzImage module file, only protected mode code need
to be loaded to guest space since the VM will boot from protected mode
directly. Futhermore, per Linux boot protocol the protected mode code
better to be aligned with kernel_alignment field in zeropage, otherwise
kernel will take time to do "rep movs" to the aligned address.
In previous code, the bzImage is loaded to the address where aligned with
kernel_alignment, this would make the protected mode code unalign with
kernel_alignment. If the kernel is configured with CONFIG_RELOCATABLE=n,
the guest would not boot. This patch fixed this issue.
Tracked-On: #6323
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
This patch moves get_bzimage_kernel_load_addr() from init_vm_sw_load() to
vm_sw_loader() stage so will set kernel load address of bzImage type kernel
in vm_bzimage_loader() in vm_load.c.
Tracked-On: #6323
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
This patch moves get_initrd_load_addr() API from init_vm_sw_load() to
vm_sw_loader() stage. The patch assumes that the kernel image have been
loaded to guest space already.
Tracked-On: #6323
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
In load_sw_modules() implementation, we always assuming the guest kernel
module has one load address and then the whole kernel image would be loaded
to guest space from its load address. This is not true when guest kernel
has multiple load addresses like ELF format kernel image.
This patch removes load_sw_modules() API, and the loading method of each
format of kernel image could be specified in prepare_loading_xxximage() API.
Tracked-On: #6323
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
As the previous commit said the kernel load address should be moved
from init_vm_sw_load() to vm_sw_loader() stage. This patch refines
the API of get_bzimage_kernel_load_addr() in init_vm_kernel_info()
for later use.
Tracked-On: #6323
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Currently the guest kernel load address and ramdisk load address are
initialized during init_vm_sw_load() stage, this is meaningless when
guest kernel has multiple segments with different loading addresses.
In that case, the kernel load addresses should be parsed and loaded
in vm_sw_loader() stage, the ramdisk load address should be set in
that stage also because it is depended on kernel load address.
This patch refines the API of get_initrd_load_addr() which will set
proper initrd load address of bzImage type kernel for later use.
Tracked-On: #6323
Signed-off-by: Victor Sun <victor.sun@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
According to PCIe Spec, for a RW register bits, If the optional feature
that is associated with the bits is not implemented, the bits are permitted
to be hardwired to 0b. However Zephyr would use INTx Line Register as writable
even this PCI device has no INTx, so emulate INTx Line Register as writable.
Tracked-On: #6330
Signed-off-by: Fei Li <fei1.li@intel.com>
There're some virtual platform which doesn't meet this constraint. So remove
this constraint.
Tracked-On: #6329
Signed-off-by: Fei Li <fei1.li@intel.com>
Update generic_board/generic_code folder with compile result
on the nuc11tnbi5 platform.
Tracked-On: #6292
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
config editor creates the default scenario xmls and launch xmls
based on generic configs when users import a new board.
Tracked-On: #6208
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
for core partition VM (like RTVM), PMC is always used for performance
profiling / tuning, so expose PMC capability and pass-through its MSRs
to the VM.
Tracked-On: #6307
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
if one array just used in local only, and its size not used extern,
use ARRAY_SIZE macro to calculate its size.
Tracked-On: #6307
Signed-off-by: Minggui Cao <minggui.cao@intel.com>
Reviewed-by: Junjie Mao <junjie.mao@intel.com>
add interface to save scenario xmls and launch xmls to user defined
path in config editor; move all config xmls and generated scripts
out of acrn-hypervisor.
Tracked-On: #6208
Signed-off-by: Shuang Zheng <shuang.zheng@intel.com>
Reviewed-by: Victor Sun <victor.sun@intel.com>
In some scenarios (e.g., nested) where lapic-pt is enabled for a vcpu
running on a pcpu hosting console timer, the hv console will be
inaccessible.
This patch adds the console callback to every VM-exit event so that the
console can still be somewhat functional under such circumstance.
Since this is VM-exit driven, the VM-exit/second can be low in certain
cases (e.g., idle or running stress workload). In extreme cases where
the guest panics/hangs, there will be no VM-exits at all.
In most cases, the shell is laggy but functional (probably enough for
debugging purpose).
Tracked-On: #6312
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
For an atomic operation using bus locking, it would generate LOCK# bus
signal, if it has Non-WB memory operand. This is an UC lock. It will
ruin the RT behavior of the system.
If MSR_IA32_CORE_CAPABILITIES[bit4] is 1, then CPU can trigger #GP
for instructions which cause UC lock. This feature is controlled by
MSR_TEST_CTL[bit28].
This patch enables #GP for guest UC lock.
Tracked-On: #6299
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Because the emulation code is for both split-lock and uc-lock,
rename splitlock.c/splitlock.h to lock_instr_emul.c/lock_instr_emul.h
Tracked-On: #6299
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Because the emulation code is for both split-lock and uc-lock, Changed
these API names:
vcpu_kick_splitlock_emulation() -> vcpu_kick_lock_instr_emulation()
vcpu_complete_splitlock_emulation() -> vcpu_complete_lock_instr_emulation()
emulate_splitlock() -> emulate_lock_instr()
Tracked-On: #6299
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
Split-lock emulation can be re-used for uc-lock. In emulate_splitlock(),
it only work if this vmexit is for #AC trap and guest do not handle
split-lock and HV enable #AC for splitlock.
Add another condition to let emulate_splitlock() also work for #GP trap
and guest do not handle uc-lock and HV enable #GP for uc-lock.
Tracked-On: #6299
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
When ACRN uses decode_instruction to emulate split-lock/uc-lock
instruction, It is actually a try-decode to see if it is XCHG.
If the instruction is XCHG instruction, ACRN must emulate it
(inject #PF if it is triggered) with peer VCPUs paused, and advance
the guest IP. If the instruction is a LOCK prefixed instruction
with accessing the UC memory, ACRN Halted the peer VCPUs, and
advance the IP to skip the LOCK prefix, and then let the VCPU
Executes one instruction by enabling IRQ Windows vm-exit. For
other cases, ACRN injects the exception back to VCPU without
emulating it.
So change the API to decode_instruction(vcpu, bool full_decode),
when full_decode is true, the API does same thing as before. When
full_decode is false, the different is if decode_instruction() meet unknown
instruction, will keep return = -1 and do not inject #UD. We can use
this to distinguish that an #UD has been skipped, and need inject #AC/#GP back.
Tracked-On: #6299
Signed-off-by: Tao Yuhong <yuhong.tao@intel.com>
While running in a nested environment, such as qemu, parse the board
information should be allowed even it is not in a native environment.
Replace the error with warning message and does not exit the program.
Tracked-On: #6208
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
Enlarge the max size to store the PTCT/RTCT table to 1k bytes
because the size of RTCT table exceeded the original max size
0x1100 - 0xF00 which makes RTCT table overlap other ACPI tables.
Tracked-On: #6303
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
1. Update the vaule of the tag CLOS_MASK to 0xfffff according to board.xml
in all scenario xml files.
2. Replace industry_launch_2uos.xml launch file with industry_launch_6uos.xml.
3. Update logical_partition.xml file.
4. Remove hybrid_rt.xml file, then add a second POST_STD_VM in hybrid.xml and
add hybrid_launch_2uos.xml launch file correspondingly.
Tracked-On: #6244
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
Add the MSI-X capability structure nodes under <capability
id="MSI-X"> in board.xml.
Example:
<capability id="MSI-X">
<table_size>16</table_size>
<table_bir>1</table_bir>
<table_offset>0x1000000</table_offset>
<pba_bir>1</pba_bir>
<pba_offset>0x0</pba_offset>
</capability>
Fix the MSI <count> nodes when there is only one vector.
Tracked-On: #6235
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
The PR 6236 has modified the board.xml format for MAX_MSIX_TABLE_NUM fix.
To compromise this PR, updates all the source file board.xmls.
Tracked-On: #6235
Signed-off-by: Kunhui-Li <kunhuix.li@intel.com>
