Implement the SBI IPI (Inter-Processor Interrupt) extension to enable
guest VMs to send software interrupts between virtual CPUs.
The implementation handles the SBI_IPI_SEND_IPI function call, which
allows a guest to target one or more vCPUs using either:
- A mask (bitmap of target harts relative to a base hart ID)
- Broadcast mode (when mask_base is UINT64_MAX)
The IPI is delivered by asserting the VS-level software interrupt
(VSSIP, bit 2) on each target vCPU. Proper validation is performed
to ensure hart IDs are within valid range and all masked harts exist.
Tracked-On: #8851
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Implement the SBI TIME (Timer) extension to allow guest VMs to program
virtual timer interrupts through the SBI interface.
The implementation handles the SBI_TIME_SET_TIMER function call, which
allows guests to set the vstimecmp CSR to schedule timer interrupts.
The vstimecmp value is written directly to the CSR and saved in the
vCPU context.
Tracked-On: #8851
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Replace SBI passthrough with proper virtualization of base extension
queries. For the Service VM, forward actual machine vendor/arch/impl
IDs from the underlying SBI. For guest VMs, provide dummy ACRN-specific
IDs to maintain isolation.
Changes:
- Return vSBI spec version 2.0 for GET_SPEC_VERSION
- Return ACRN implementation ID (55) and version for GET_IMP_ID/GET_IMP_VERSION
- Forward real mvendorid/marchid/mimpid to Service VM
- Provide dummy vendor/arch/impl IDs (0/0/0) to guest VMs
- Store machine IDs in vm_arch structure during VM initialization
- Remove unnecessary SBI passthrough for base extension queries
This provides better isolation and control over the virtual SBI
interface exposed to guests.
Tracked-On: #8851
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Add wrapper functions to query machine vendor ID (mvendorid),
architecture ID (marchid), and implementation ID (mimpid) through
the SBI base extension.
These IDs identify the RISC-V processor vendor, microarchitecture,
and specific implementation respectively. The hypervisor needs to
retrieve these values from the underlying SBI firmware to forward
them to the Service VM via vSBI, allowing the Service VM to see
the actual hardware characteristics.
Tracked-On: #8851
Signed-off-by: Haoyu Tang <haoyu.tang@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Add virtual interrupt injection infrastructure for RISC-V hypervisor.
Implement vcpu_set_intr() and vcpu_clear_intr() to manage virtual
interrupt pending state by updating irqs_pending bitmap.
Add vcpu_inject_pending_intr() to inject pending interrupts into
VS-mode by updating HVIP CSR with atomic operations.
Tracked-On: #8844
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Add virtual exception handling infrastructure for RISC-V hypervisor
and enables proper virtualization of RISC-V exceptions by allowing
the hypervisor to inject exceptions into guest VS-mode.
- Implement vcpu_set_trap() to inject traps to VS-mode
- Implement vcpu_queue_exception() to queue exceptions for vCPU injection
- Process pending exception requests in riscv_process_vcpu_requests()
v1->v2:
change vcpu_redirect_trap -> vcpu_set_trap
Tracked-On: #8844
Signed-off-by: Yi Y Sun <yi.y.sun@intel.com>
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Command line specifies sbi DBCN both as early console and
console (if no other hvc is provided, hvc0 will be registered as
riscv_hvc_sbi).
Note that console=hvc0 requires kernel to enable two configs:
CONFIG_HVC_RISCV_SBI=y
CONFIG_NONPORTABLE=y (dependency of the first one)
Tracked-On: #8841
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Use bvt for shared scenario and adds hybrid scenario where one
pre-launched and one service-vm is configured.
Tracked-On: #8841
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
RISC-V vcpu capability is represented by an ISA extension string.
Add API to adjust this string for virtual FDT.
Tracked-On: #8841
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Currently dbcn outputs directly to console. Outputs to ACRN
shell vm_console when other dependencies are ready.
Tracked-On: #8841
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Initialize Service VM vFDT by reserving hypervisor and pre-launched VM
memory regions.
The vFDT is copied to Service VM to the place just before the kernel
load address, and this needs to be fixed later when MMU module is
implemented.
Tracked-On: #8841
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
This patch adds ACRN-side APIs that uses libfdt to manupulate
FDT. This patch implements two APIs: read physical memory range
(assuming it is one continous physical range), and read reserved
memory ranges (multiple reserved memory ranges may present).
Tracked-On: #8841
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Original interrupt context save/restore routine saves to/restore from
per-cpu stack. This commit modifies it to support saving to/restoring
from address pointed to by sscratch register.
When sscratch is 0, the assembly is functionally equivalent to the
old version (save to/restore from per-cpu stack)
When sscratch is not 0, the assembly saves to/restores from the place
that sscratch points to.
hstatus is also added to the trap frame as this affects the virtual
mode the trap returns to.
Tracked-On: #8841
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Unlike x86 which explicitly distinguishes guest traps and host traps (VM
exits vs. IDT trap gates), risc-v unifies them to a single trap gate
with bits in multiple CSRs representing the privilege mode before the
trap. This commit follows this design.
Due to this change the arch_vcpu_thread in risc-v was basically
abandoned, and used only as a first-time entry point to guest, with the
rest of the original x86 arch_vcpu_thread being re-implemented following
above single-entry design.
Save/restore routine is also being re-implemented to account for
both hs-mode traps and v-mode traps. sscratch is used to mark the place
where the context is being saved to/restored from. When sscratch is
zero at the time of the trap, the context is saved into host stack.
When sscratch is non-zero, the context is saved to vcpu->arch.regs
(similar for restore).
Tracked-On: #8841
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
This patch integrates RISC-V with the common IRQ framework:
- Register software and timer interrupt handlers via request_irq().
- Refine dispatch_interrupt() to handle interrupts via do_irq().
Tracked-On: #8845
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Include the common IRQ header rather than the arch-specific version.
This follows the style we defined for multi-arch development.
Remaining RISC-V related files will be updated in later patches when
integration with the common IRQ framework is implemented.
Tracked-On: #8845
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Move NR_IRQS from the common header to arch-specific headers since its
value differs between architectures.
- On x86, it is 256.
- On RISC-V, it includes both CPU interrupts and external interrupts
(from PLIC, APLIC, etc.).
Tracked-On: #8845
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Move the declarations of arch-specific IRQ functions from their
arch-specific headers into the common header file.
Also rename these functions from xxx_arch() to arch_xxx() for better
naming consistency across architectures.
This change follows the style defined for multi-arch development.
Tracked-On: #8845
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
This patch fixes two bugs. The reason for writing them
into one commit is that they are related and the fixes
change the same places.
The first bug:
The size of struct stack_frame is 0x78, not 0x80, but
the save/restore assembly routine allocates/deallocates
the size of stack frame by 0x80.
The vcpu thread stack is initialized by allocating
sizeof(struct stack_frame) from the top of the stack
and put initial values there (arch_build_stack_frame).
The vcpu thread stack will underflow at the first
time this thread gets scheduled. So the fix is to change
the 0x80 to 0x78 in save/restore routine.
The second bug:
Save/restore routine needs to capture sstatus, as different
threads might have different interrupt enabling settings.
For example, vcpu threads always get scheduled out when the
interrupts are disabled, but idle thread needs to have the
interrupts enabled. So sstatus needs to be saved/restored.
The fix is to add a new member sstatus in struct stack_frame.
Adding a new member in struct stack_frame boost the size
of struct stack_frame to 0x80, which in this case the fix
of the first bug is no longer needed.
Tracked-On: #8838
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
There are two reasons to use inline functions and numbered-CSR
instead of simply string concat.
1, With old style, CSR names have to be written in lower cases
and cannot prefix anything. This sometimes causes confusion with
variables. For example, csr_write(sstatus, sstatus). Changing to
inline function with MACROs can reduce confusion:
csr_write(CSR_SSTATUS, sstatus)
2, Using number macros allows us to manage CSRs in a more organized
way. We can now put CSR names in variables or arrays and access them
using variables instead of just string names.
Tracked-On: #8838
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Adds csr read/write/set/clear/read_set/read_clear/swap utilities.
Also adds definitions for CSRs.
Tracked-On: #8838
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Pre-launched VM needs to load pre-compiled FDT binary (which is the same
when it needs pre-compiled ACPI binary).
Tracked-On: #8838
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Just as we accept pre-compiled ACPI binary for pre-launched VM, this
commit adds support for pre-launched VM to accept pre-compiled FDT
binary with default tag FDT_VMx, where x is the VM id.
Tracked-On: #8838
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Bare boot protocol is a protocol to be used when there are no protocols
(such as multiboot1/2) are available: ACRN have no way to know where its
modules are being loaded, how large they are, and what are their command
line arguments.
Bare boot protocol allows you to pre-configure (hard-code) modules' address and
sizes. ACRN will find modules based on the pre-configured information
without the need of a bootloader passing information to it.
Tracked-On: #8838
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
This option controls whether runtime FDT parsing
is enabled. If off, hypervisor needs to use static configuration
information from config-tool.
Tracked-On: #8838
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
Besides implementing copy_from/to_gpa, this commit also wraps a dummy
commit in mmu.c that exposes API of adding hv mmu mapping.
Tracked-On: #8830
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
We may not need this for every architecture. Conditionally
wraps it.
Tracked-On: #8830
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
