This patch adds the logic needed to fully parse an SR-IOV extended
capability structure. Such information will later be used to extract all
information about physical and virtual functions.
Tracked-On: #7301
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
In order to ease the access of certain capability structure of a PCI config
space, this patch changes the class PCIConfigSpace to maintain a
_caps_as_dict dictionary that maps capability names (as specified in the
caps.py and extcaps.py) to the actual capability structures.
Tracked-On: #7301
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Many of the license and Intel copyright headers include the "All rights
reserved" string. It is not relevant in the context of the BSD-3-Clause
license that the code is released under. This patch removes those strings
throughout the code (hypervisor, devicemodel and misc).
Tracked-On: #7254
Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
Today we assume a device node under /sys/devices/pciXXXX:XX/ always contain
a `config` file which shows the configuration space of the PCI
functions. This seems not the case for, at least, Non-Transparent
Bridge (or NTB).
This patch checks the existence of the `config` file and skips PCI
functions which do not contain one.
Tracked-On: #6902
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
According to PCIe specification (since 2.0), absence of any extended
capabilities is required to be indicated by an extended capability header
with a capability ID of FFFFh and a next capability offset of 000h. Thus,
the board inspector today accesses the first extended capability header at
100h in the configuration space of a PCIe function unconditionally.
However, in practice we have seen real PCI functions which has a PCIe
capability but no extended capability header. This will cause the board
inspector to crash due to invalid configuration space accesses.
To fix that, this patch adds a check to the size of the configuration space
before walking the extended capabilities of a PCIe function.
Tracked-On: #6411
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Anthony Xu <anthony.xu@intel.com>
1. "make clean && make BOARD=nuc11tnbi5 SCENARIO=shared" will generate the acrn debian package.
2. "make clean && make board_inspector" will generate the acrn board_inspector debian package
Tracked-On: #6688
Signed-off-by: Hu Fenglin <fenglin.hu@intel.com>
It is seen that the BAR in the PCI configuration space of a device can be
cleared when the device is put to D3. This patch resumes a device not in D0
before parsing its configuration space in order to collect accurate
information.
This patch is added in v2 of the series.
Tracked-On: #6287
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Add the MSI-X capability structure nodes under <capability
id="MSI-X"> in board.xml.
Example:
<capability id="MSI-X">
<table_size>16</table_size>
<table_bir>1</table_bir>
<table_offset>0x1000000</table_offset>
<pba_bir>1</pba_bir>
<pba_offset>0x0</pba_offset>
</capability>
Fix the MSI <count> nodes when there is only one vector.
Tracked-On: #6235
Signed-off-by: Yang,Yu-chu <yu-chu.yang@intel.com>
This patch extracts information on devices and put them under the
`/acrn-config/devices` node in the board XML.
The generated XML looks like the following:
<devices>
<bus type="system">
<acpi_object>\_SB_</acpi_object>
<bus id="PNP0A08" type="pci" address="0x0" description="...">
<vendor>0x8086</vendor>
<identifier>0x591f</identifier>
<subsystem_vendor>0x1028</subsystem_vendor>
<subsystem_identifier>0x07a1</subsystem_identifier>
<class>0x060000</class>
<acpi_object>\_SB_.PCI0</acpi_object>
<resource type="bus_number" min="0x0" max="0x3e" len="0x3f"/>
<resource type="io_port" min="0x0" max="0xcf7" len="0xcf8"/>
<resource type="io_port" min="0xcf8" max="0xcf8" len="0x8"/>
<resource type="io_port" min="0xd00" max="0xffff" len="0xf300"/>
<resource type="memory" min="0x10000" max="0x1ffff" len="0x0"/>
<resource type="memory" min="0xa0000" max="0xbffff" len="0x20000"/>
<resource type="memory" min="0xc0000" max="0xc3fff" len="0x4000"/>
<resource type="memory" min="0xc4000" max="0xc7fff" len="0x4000"/>
...
<capability id="vendor_specific"/>
<device address="0x1"> ... </device>
...
<bus>
<bus>
<device> ... <device>
<devices>
The hierarchy of devices are based on the hierarchy of device objects in
the ACPI namespace (which is established by interpreting the ACPI DSDT and
SSDT tables). Typically most device objects are under the predefined
`_SB_` (i.e. System Bus) object under which an object representing the PCI
root complex (`\_SB_.PCI0` in the example above) can be found. The PCI
devices attached to bus 0 are listed as children of the PCI root complex
node.
For each bus or device, the board inspector tries best to parse the
information from both ACPI device objects and PCI configuration space to
extract the following:
- the model (via `_HID` object and PCI vendor ID, device ID and class code),
- assigned resources (via `_CRS` object and PCI BARs),
- capabilities (via the PCI capability list)
v1 -> v2:
- Fix references to undeclared modules or variables.
- Make the ACPI extractor advanced and not enabled by default.
- Extract the secondary I/O and memory-mapped I/O addresses of bridges.
Tracked-On: #5922
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
This patch adds a parser of PCI-compatible configuration space read from
sysfs. The headers and capability lists are fully parsed, but only a couple
of capabilities are parsed completely. Parsing of additional capabilities
will be added on an on-demand basis.
v1 -> v2:
- Fix a typo that causes incorrect parsing of BAR types
- Parse capability structures using from_buffer_copy instead of
from_address
Tracked-On: #5922
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
