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https://github.com/projectacrn/acrn-hypervisor.git
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5fa816f921
The added parse_ptct function will parse native ACPI PTCT table to acquire information like pSRAM location/size/level and PTCM location, and save them. Tracked-On: #5330 Signed-off-by: Qian Wang <qian1.wang@intel.com>
54 lines
1.1 KiB
C
54 lines
1.1 KiB
C
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PTCT_H
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#define PTCT_H
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#include <acpi.h>
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#define PTCT_ENTRY_TYPE_PTCD_LIMIT 1U
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#define PTCT_ENTRY_TYPE_PTCM_BINARY 2U
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#define PTCT_ENTRY_TYPE_WRC_L3_MASKS 3U
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#define PTCT_ENTRY_TYPE_GT_L3_MASKS 4U
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#define PTCT_ENTRY_TYPE_PSRAM 5U
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#define PTCT_ENTRY_TYPE_STREAM_DATAPATH 6U
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#define PTCT_ENTRY_TYPE_TIMEAWARE_SUBSYS 7U
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#define PTCT_ENTRY_TYPE_RT_IOMMU 8U
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#define PTCT_ENTRY_TYPE_MEM_HIERARCHY_LATENCY 9U
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#define PSRAM_BASE_HPA 0x40080000U
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#define PSRAM_BASE_GPA 0x40080000U
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#define PSRAM_MAX_SIZE 0x00800000U
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struct ptct_entry{
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uint16_t size;
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uint16_t format;
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uint32_t type;
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uint32_t data[64];
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} __packed;
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struct ptct_entry_data_ptcm_binary
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{
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uint64_t address;
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uint32_t size;
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} __packed;
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struct ptct_entry_data_psram
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{
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uint32_t cache_level;
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uint64_t base;
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uint32_t ways;
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uint32_t size;
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uint32_t apic_id_0; /*only the first core is responsible for initialization of L3 mem region*/
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} __packed;
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extern uint64_t psram_area_bottom;
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extern uint64_t psram_area_top;
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#endif /* PTCT_H */
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