Yin Fengwei 7edf929a69 hv: trap vm0 write/read pm1a/pm1b registers ... ACRN needs to trap the pm1a/pm1b written/read from VM0. So we could know when should we put the system to S3. We will have two path back to VM0: - S3 enter/exit sucess. Will reset VM0 and jump to VM0 wakeup vec with real mode - S3 enter/exit failed. Will return to the next instruction of pm1a/pm1b register writing. VM0 will read the pm1a/pm1b evt register to check whether it's waked up or not. Signed-off-by: Victor Sun <victor.sun@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2018-06-28 13:12:54 +08:00
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x86	hv: trap vm0 write/read pm1a/pm1b registers	2018-06-28 13:12:54 +08:00