Yin Fengwei 7edf929a69 hv: trap vm0 write/read pm1a/pm1b registers ... ACRN needs to trap the pm1a/pm1b written/read from VM0. So we could know when should we put the system to S3. We will have two path back to VM0: - S3 enter/exit sucess. Will reset VM0 and jump to VM0 wakeup vec with real mode - S3 enter/exit failed. Will return to the next instruction of pm1a/pm1b register writing. VM0 will read the pm1a/pm1b evt register to check whether it's waked up or not. Signed-off-by: Victor Sun <victor.sun@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2018-06-28 13:12:54 +08:00
..
guest_pm.h	hv: trap vm0 write/read pm1a/pm1b registers	2018-06-28 13:12:54 +08:00
guest.h	guest.h: Condition operator fix of foreach_vcpu loop	2018-06-26 12:29:08 +08:00
ucode.h	license: Replace license text with SPDX tag	2018-06-01 10:43:06 +08:00
vcpu.h	hv: cpu_context is not only used by guest.	2018-06-25 17:29:45 +08:00
vioapic.h	fix parted of "missing for discarded return value"	2018-06-19 16:21:45 +08:00
vlapic.h	HV: treewide: enforce unsignedness of pcpu_id	2018-06-21 16:59:21 +08:00
vm.h	hv: add function to return to VM0	2018-06-28 13:12:54 +08:00
vpic.h	HV: irq: convert hexadecimals used in bitops to unsigned	2018-06-21 13:12:39 +08:00