mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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bae19f5f1f
Original interrupt context save/restore routine saves to/restore from per-cpu stack. This commit modifies it to support saving to/restoring from address pointed to by sscratch register. When sscratch is 0, the assembly is functionally equivalent to the old version (save to/restore from per-cpu stack) When sscratch is not 0, the assembly saves to/restores from the place that sscratch points to. hstatus is also added to the trap frame as this affects the virtual mode the trap returns to. Tracked-On: #8841 Signed-off-by: Yifan Liu <yifan1.liu@intel.com> Signed-off-by: Haicheng Li <haicheng.li@intel.com> Acked-by: Wang Yu1 <yu1.wang@intel.com>
153 lines
3.6 KiB
ArmAsm
153 lines
3.6 KiB
ArmAsm
/*
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* Copyright (C) 2023-2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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#include <asm/trap.h>
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#include <cpu.h>
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.macro cpu_ctx_save
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/* General purpose registers. */
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sd sp, CPU_REGS_OFFSET_SP(t0)
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sd ra, CPU_REGS_OFFSET_RA(t0)
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sd gp, CPU_REGS_OFFSET_GP(t0)
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sd tp, CPU_REGS_OFFSET_TP(t0)
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sd t1, CPU_REGS_OFFSET_T1(t0)
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sd t2, CPU_REGS_OFFSET_T2(t0)
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sd s0, CPU_REGS_OFFSET_S0(t0)
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sd s1, CPU_REGS_OFFSET_S1(t0)
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sd a0, CPU_REGS_OFFSET_A0(t0)
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sd a1, CPU_REGS_OFFSET_A1(t0)
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sd a2, CPU_REGS_OFFSET_A2(t0)
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sd a3, CPU_REGS_OFFSET_A3(t0)
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sd a4, CPU_REGS_OFFSET_A4(t0)
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sd a5, CPU_REGS_OFFSET_A5(t0)
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sd a6, CPU_REGS_OFFSET_A6(t0)
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sd a7, CPU_REGS_OFFSET_A7(t0)
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sd s2, CPU_REGS_OFFSET_S2(t0)
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sd s3, CPU_REGS_OFFSET_S3(t0)
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sd s4, CPU_REGS_OFFSET_S4(t0)
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sd s5, CPU_REGS_OFFSET_S5(t0)
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sd s6, CPU_REGS_OFFSET_S6(t0)
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sd s7, CPU_REGS_OFFSET_S7(t0)
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sd s8, CPU_REGS_OFFSET_S8(t0)
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sd s9, CPU_REGS_OFFSET_S9(t0)
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sd s10, CPU_REGS_OFFSET_S10(t0)
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sd s11, CPU_REGS_OFFSET_S11(t0)
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sd t3, CPU_REGS_OFFSET_T3(t0)
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sd t4, CPU_REGS_OFFSET_T4(t0)
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sd t5, CPU_REGS_OFFSET_T5(t0)
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sd t6, CPU_REGS_OFFSET_T6(t0)
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/* Control and Status Registers (CSRs). */
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csrr t1, sstatus
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sd t1, CPU_REGS_OFFSET_STATUS(t0)
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csrr t2, scause
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sd t2, CPU_REGS_OFFSET_CAUSE(t0)
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csrr t3, stval
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sd t3, CPU_REGS_OFFSET_TVAL(t0)
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csrr t4, sscratch
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sd t4, CPU_REGS_OFFSET_T0(t0)
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csrr t5, sepc
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sd t5, CPU_REGS_OFFSET_EPC(t0)
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.endm
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.macro cpu_ctx_restore
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/* Control and Status Registers (CSRs). */
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ld t1, CPU_REGS_OFFSET_EPC(t0)
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csrw sepc, t1
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ld t2, CPU_REGS_OFFSET_STATUS(t0)
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csrw sstatus, t2
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/* General purpose registers. */
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ld sp, CPU_REGS_OFFSET_SP(t0)
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ld ra, CPU_REGS_OFFSET_RA(t0)
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ld gp, CPU_REGS_OFFSET_GP(t0)
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ld tp, CPU_REGS_OFFSET_TP(t0)
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ld t1, CPU_REGS_OFFSET_T1(t0)
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ld t2, CPU_REGS_OFFSET_T2(t0)
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ld s0, CPU_REGS_OFFSET_S0(t0)
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ld s1, CPU_REGS_OFFSET_S1(t0)
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ld a0, CPU_REGS_OFFSET_A0(t0)
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ld a1, CPU_REGS_OFFSET_A1(t0)
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ld a2, CPU_REGS_OFFSET_A2(t0)
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ld a3, CPU_REGS_OFFSET_A3(t0)
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ld a4, CPU_REGS_OFFSET_A4(t0)
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ld a5, CPU_REGS_OFFSET_A5(t0)
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ld a6, CPU_REGS_OFFSET_A6(t0)
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ld a7, CPU_REGS_OFFSET_A7(t0)
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ld s2, CPU_REGS_OFFSET_S2(t0)
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ld s3, CPU_REGS_OFFSET_S3(t0)
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ld s4, CPU_REGS_OFFSET_S4(t0)
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ld s5, CPU_REGS_OFFSET_S5(t0)
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ld s6, CPU_REGS_OFFSET_S6(t0)
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ld s7, CPU_REGS_OFFSET_S7(t0)
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ld s8, CPU_REGS_OFFSET_S8(t0)
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ld s9, CPU_REGS_OFFSET_S9(t0)
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ld s10, CPU_REGS_OFFSET_S10(t0)
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ld s11, CPU_REGS_OFFSET_S11(t0)
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ld t3, CPU_REGS_OFFSET_T3(t0)
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ld t4, CPU_REGS_OFFSET_T4(t0)
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ld t5, CPU_REGS_OFFSET_T5(t0)
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ld t6, CPU_REGS_OFFSET_T6(t0)
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ld t0, CPU_REGS_OFFSET_T0(t0)
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.endm
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.macro cpu_host_state_load
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ld sp, CPU_REGS_OFFSET_EXC_SP(t0)
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ld tp, CPU_REGS_OFFSET_HOST_TP(t0)
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ld gp, CPU_REGS_OFFSET_HOST_GP(t0)
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.endm
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.macro cpu_host_state_save
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sd sp, CPU_REGS_OFFSET_EXC_SP(t0)
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sd tp, CPU_REGS_OFFSET_HOST_TP(t0)
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sd gp, CPU_REGS_OFFSET_HOST_GP(t0)
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.endm
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.text
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.balign 4
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.globl strap_handler
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strap_handler:
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/*
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* sscratch == 0: trap comes from hs-mode
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* sscratch != 0: trap comes from v-mode, and sscratch points to struct acrn_vcpu_arch
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*/
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csrrw t0, sscratch, t0
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bnez t0, vcpu_exit_trap
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addi sp, sp, -CPU_REGS_OFFSET_LAST
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mv t0, sp
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cpu_ctx_save
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csrw sscratch, zero
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/** Pass t0 in a0, as the argument to dispatch_trap(). */
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mv a0, t0
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call dispatch_trap
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mv t0, sp
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cpu_ctx_restore
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addi sp, sp, CPU_REGS_OFFSET_LAST
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sret
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vcpu_exit_trap:
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cpu_ctx_save
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cpu_host_state_load
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csrw sscratch, zero
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/* t0 points to struct acrn_vcpu_arch */
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mv a0, t0
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call dispatch_vcpu_trap
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.globl vcpu_exit_return
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vcpu_exit_return:
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csrr t0, sscratch
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cpu_host_state_save
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cpu_ctx_restore
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sret
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