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https://github.com/projectacrn/acrn-hypervisor.git
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8c2e8a6b5d
Unlike x86 which explicitly distinguishes guest traps and host traps (VM exits vs. IDT trap gates), risc-v unifies them to a single trap gate with bits in multiple CSRs representing the privilege mode before the trap. This commit follows this design. Due to this change the arch_vcpu_thread in risc-v was basically abandoned, and used only as a first-time entry point to guest, with the rest of the original x86 arch_vcpu_thread being re-implemented following above single-entry design. Save/restore routine is also being re-implemented to account for both hs-mode traps and v-mode traps. sscratch is used to mark the place where the context is being saved to/restored from. When sscratch is zero at the time of the trap, the context is saved into host stack. When sscratch is non-zero, the context is saved to vcpu->arch.regs (similar for restore). Tracked-On: #8841 Signed-off-by: Yifan Liu <yifan1.liu@intel.com> Signed-off-by: Haicheng Li <haicheng.li@intel.com> Acked-by: Wang Yu1 <yu1.wang@intel.com>
107 lines
4.0 KiB
C
107 lines
4.0 KiB
C
/*
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* Copyright (C) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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#ifndef RISCV_TRAP_H
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#define RISCV_TRAP_H
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#define TRAP_VECTOR_MODE_DIRECT 0U
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#define TRAP_VECTOR_MODE_VECTORED 1U
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/**
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* The Interrupt bit (most significant bit) in the scause register
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* is set if the trap was caused by an interrupt.
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*/
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#define TRAP_CAUSE_INTERRUPT_BITMASK (1UL << 63U)
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#define TRAP_CAUSE_EXC_MISALIGNED_FETCH 0x0
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#define TRAP_CAUSE_EXC_FETCH_ACCESS 0x1
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#define TRAP_CAUSE_EXC_ILLEGAL_INSTRUCTION 0x2
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#define TRAP_CAUSE_EXC_BREAKPOINT 0x3
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#define TRAP_CAUSE_EXC_MISALIGNED_LOAD 0x4
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#define TRAP_CAUSE_EXC_LOAD_ACCESS 0x5
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#define TRAP_CAUSE_EXC_MISALIGNED_STORE 0x6
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#define TRAP_CAUSE_EXC_STORE_ACCESS 0x7
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#define TRAP_CAUSE_EXC_USER_ECALL 0x8
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#define TRAP_CAUSE_EXC_SUPERVISOR_ECALL 0x9
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#define TRAP_CAUSE_EXC_VIRTUAL_SUPERVISOR_ECALL 0xa
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#define TRAP_CAUSE_EXC_MACHINE_ECALL 0xb
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#define TRAP_CAUSE_EXC_FETCH_PAGE_FAULT 0xc
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#define TRAP_CAUSE_EXC_LOAD_PAGE_FAULT 0xd
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#define TRAP_CAUSE_EXC_STORE_PAGE_FAULT 0xf
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#define TRAP_CAUSE_EXC_DOUBLE_TRAP 0x10
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#define TRAP_CAUSE_EXC_SW_CHECK_EXCP 0x12
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#define TRAP_CAUSE_EXC_FETCH_GUEST_PAGE_FAULT 0x14
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#define TRAP_CAUSE_EXC_LOAD_GUEST_PAGE_FAULT 0x15
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#define TRAP_CAUSE_EXC_VIRTUAL_INST_FAULT 0x16
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#define TRAP_CAUSE_EXC_STORE_GUEST_PAGE_FAULT 0x17
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/* Trap Cause Codes - Interrupt */
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/* Software Interrupt */
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#define TRAP_CAUSE_IRQ_S_SOFT 1UL /* Supervisor software interrupt */
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#define TRAP_CAUSE_IRQ_VS_SOFT 2UL /* Virtual supervisor software interrupt */
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#define TRAP_CAUSE_IRQ_M_SOFT 3UL /* Machine software interrupt */
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/* Timer Interrupt */
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#define TRAP_CAUSE_IRQ_S_TIMER 5UL /* Supervisor timer interrupt */
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#define TRAP_CAUSE_IRQ_VS_TIMER 6UL /* Virtual supervisor timer interrupt */
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#define TRAP_CAUSE_IRQ_M_TIMER 7UL /* Machine timer interrupt */
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/* External Interrupt */
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#define TRAP_CAUSE_IRQ_S_EXT 9UL /* Supervisor external interrupt */
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#define TRAP_CAUSE_IRQ_VS_EXT 10UL /* Virtual supervisor external interrupt */
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#define TRAP_CAUSE_IRQ_M_EXT 11UL /* Machine external interrupt */
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#define TRAP_CAUSE_IRQ_S_GUEST_EXT 12UL /* Supervisor guest external interrupt */
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#define TRAP_CAUSE_IRQ_COUNTER_OVF 13UL /* Reserved for counter-overflow interrupt */
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/* Interrupt Pending/Enable registers flags */
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/* Software Interrupt */
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#define IP_IE_SSI (1UL << TRAP_CAUSE_IRQ_S_SOFT)
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#define IP_IE_VSSI (1UL << TRAP_CAUSE_IRQ_VS_SOFT)
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#define IP_IE_MSI (1UL << TRAP_CAUSE_IRQ_M_SOFT)
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/* Timer Interrupt */
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#define IP_IE_STI (1UL << TRAP_CAUSE_IRQ_S_TIMER)
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#define IP_IE_VSTI (1UL << TRAP_CAUSE_IRQ_VS_TIMER)
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#define IP_IE_MTI (1UL << TRAP_CAUSE_IRQ_M_TIMER)
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/* External Interrupt */
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#define IP_IE_SEI (1UL << TRAP_CAUSE_IRQ_S_EXT)
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#define IP_IE_VSEI (1UL << TRAP_CAUSE_IRQ_VS_EXT)
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#define IP_IE_MEI (1UL << TRAP_CAUSE_IRQ_M_EXT)
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#define IP_IE_SGEI (1UL << TRAP_CAUSE_IRQ_S_GUEST_EXT)
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#define IP_IE_LCOFI (1UL << TRAP_CAUSE_IRQ_COUNTER_OVF)
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#define HEDELEG_DEFAULT \
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((1UL << TRAP_CAUSE_EXC_MISALIGNED_FETCH) | \
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(1UL << TRAP_CAUSE_EXC_MISALIGNED_LOAD) | \
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(1UL << TRAP_CAUSE_EXC_MISALIGNED_STORE) | \
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(1UL << TRAP_CAUSE_EXC_BREAKPOINT) | \
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(1UL << TRAP_CAUSE_EXC_ILLEGAL_INSTRUCTION) | \
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(1UL << TRAP_CAUSE_EXC_USER_ECALL) | \
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(1UL << TRAP_CAUSE_EXC_FETCH_ACCESS) | \
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(1UL << TRAP_CAUSE_EXC_LOAD_ACCESS) | \
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(1UL << TRAP_CAUSE_EXC_STORE_ACCESS) | \
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(1UL << TRAP_CAUSE_EXC_FETCH_PAGE_FAULT) | \
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(1UL << TRAP_CAUSE_EXC_LOAD_PAGE_FAULT) | \
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(1UL << TRAP_CAUSE_EXC_STORE_PAGE_FAULT))
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#define HIDELEG_DEFAULT \
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((1UL << TRAP_CAUSE_IRQ_VS_SOFT) | \
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(1UL << TRAP_CAUSE_IRQ_VS_EXT) | \
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(1UL << TRAP_CAUSE_IRQ_VS_TIMER))
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#ifndef ASSEMBLER
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#include <irq.h>
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extern uint64_t strap_handler;
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extern void vcpu_exit_return(void);
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void dispatch_interrupt(const struct intr_excp_ctx *ctx);
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void dispatch_trap(const struct intr_excp_ctx *ctx);
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void s_sw_irq_handler(__unused uint32_t irq, __unused void *data);
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#endif /* ASSEMBLER */
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#endif /* RISCV_TRAP_H */
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