acrn-hypervisor/devicemodel/hw/pci
Jian Jun Chen 29b1ebcd43 dm: add support of high MMIO mapping
1G PCI hole is added just after 4G address which is used as the
PCI high MMIO address space. Guest high memory is mapped from 5G
address for both EPT and device model user space address. Guest
e820 table and API vm_map_gpa are updated accordingly.

Tracked-On: #2577
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Yu Wang <yu1.wang@intel.com>
2019-02-28 18:33:11 +08:00
..
virtio dm: add support of high MMIO mapping 2019-02-28 18:33:11 +08:00
ahci.c dm: storage: rename delete to discard 2018-12-18 13:21:07 +08:00
core.c dm: add support of high MMIO mapping 2019-02-28 18:33:11 +08:00
gsi_sharing.c dm: hw: Replace sscanf with permitted string API 2018-12-17 19:17:29 +08:00
gvt.c dm: Fix some issues from string operations 2018-12-25 18:40:04 +08:00
hostbridge.c
irq.c DM: wrap ASSERT/DEASSERT IRQ line with Set/Clear IRQ line 2018-10-29 09:26:23 +08:00
lpc.c dm: refine the uart_core 2018-12-27 09:58:20 +08:00
npk.c dm: Fix some issues from string operations 2018-12-25 18:40:04 +08:00
passthrough.c dm: passthru: add error handling if msix table init failed 2018-12-20 09:08:37 +08:00
platform_gsi_info.c
uart.c dm: refine the uart_core 2018-12-27 09:58:20 +08:00
wdt_i6300esb.c dm: provide timer callback handlers the number of expirations 2019-01-23 10:33:28 +08:00
xhci.c DM: xHCI: array bound checking before it is used 2019-01-03 22:42:40 +08:00