Li Fei1 e3f2f98c66 hv: virq: refine pending event inject sequence ...

Inject pending exception prior pending interrupt to complete the previous instruction.

Tracked-On: #1842
Signed-off-by: Li Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>

2020-06-01 13:16:54 +08:00

..

arch/x86

hv: virq: refine pending event inject sequence

2020-06-01 13:16:54 +08:00

common

HV: support up to 7 post launched VMs for industry scenario

2020-04-20 23:58:58 +08:00

debug

HV: correct ept page array usage

2020-03-12 14:56:34 +08:00

dm

hv: vioapic init for SOS VM on platforms with multiple IO-APICs

2020-04-13 11:39:58 +08:00

hw

hv: vpci: pass through stolen memory and opregion memory for GVT-D

2020-03-11 10:59:23 +08:00

lib

hv: support xsave in context switch

2019-12-02 09:31:12 +08:00

public

hv: dynamically configure CPU affinity through hypercall

2020-04-23 10:59:08 +08:00