Yin Fengwei d0e06c4f80 hv: debug: Enable MMIO UART support ... New board, EHL CRB, does not have legacy port IO UART. Even the PCI UART are not work due to BIOS's bug workaround(the BARs on LPSS PCI are reset after BIOS hand over control to OS). For ACRN console usage, expose the debug UART via ACPI PnP device (access by MMIO) and add support in hypervisor debug code. Another special thing is that register width of UART of EHL CRB is 1byte. Introduce reg_width for each struct console_uart. Tracked-On: #4937 Signed-off-by: Yin Fengwei <fengwei.yin@intel.com> Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>		2020-08-27 13:31:17 +08:00
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console.h	HV: vuart: remove console related code from vuart	2019-04-29 15:25:39 +08:00
dbg_cmd.h	hv:cleanup console.h	2019-02-27 11:12:48 +08:00
dump.h
logmsg.h	hv: rename the ACRN_DBG_XXX	2020-01-14 10:21:23 +08:00
npk_log.h	hv: clean up function definitions in npk_log.h	2018-11-28 14:57:49 +08:00
profiling_internal.h	HV: correct ept page array usage	2020-03-12 14:56:34 +08:00
profiling.h	profiling: split profiling_vmexit_handler into two functions	2018-12-14 08:54:30 +08:00
sbuf.h	hv: bugfix for sbuf reset	2019-06-27 15:40:19 +08:00
shell.h	hv:cleanup console.h	2019-02-27 11:12:48 +08:00
trace.h	hv: clean up function definitions in trace.h	2018-11-28 14:57:49 +08:00
uart16550.h	hv: debug: Enable MMIO UART support	2020-08-27 13:31:17 +08:00