mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-04-29 20:24:00 +00:00
9e8c1a1508
ACRN get messy default values for some CAT CBM MSRs, these unexpected default value will result in TCC Software SRAM initializes crash. This patch resets above error default values before calling CRL(cache reserve library) ABI initializaion function. Tracked-On: #6780 Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
169 lines
5.7 KiB
C
169 lines
5.7 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/*
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* cpuid.h
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*
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* Created on: Jan 4, 2018
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* Author: don
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*/
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#ifndef CPUID_H_
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#define CPUID_H_
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/* CPUID bit definitions */
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#define CPUID_ECX_SSE3 (1U<<0U)
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#define CPUID_ECX_PCLMUL (1U<<1U)
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#define CPUID_ECX_DTES64 (1U<<2U)
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#define CPUID_ECX_MONITOR (1U<<3U)
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#define CPUID_ECX_DS_CPL (1U<<4U)
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#define CPUID_ECX_VMX (1U<<5U)
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#define CPUID_ECX_SMX (1U<<6U)
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#define CPUID_ECX_EST (1U<<7U)
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#define CPUID_ECX_TM2 (1U<<8U)
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#define CPUID_ECX_SSSE3 (1U<<9U)
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#define CPUID_ECX_CID (1U<<10U)
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#define CPUID_ECX_SDBG (1U<<11U)
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#define CPUID_ECX_FMA (1U<<12U)
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#define CPUID_ECX_CX16 (1U<<13U)
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#define CPUID_ECX_ETPRD (1U<<14U)
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#define CPUID_ECX_PDCM (1U<<15U)
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#define CPUID_ECX_DCA (1U<<18U)
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#define CPUID_ECX_SSE4_1 (1U<<19U)
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#define CPUID_ECX_SSE4_2 (1U<<20U)
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#define CPUID_ECX_x2APIC (1U<<21U)
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#define CPUID_ECX_MOVBE (1U<<22U)
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#define CPUID_ECX_POPCNT (1U<<23U)
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#define CPUID_ECX_AES (1U<<25U)
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#define CPUID_ECX_XSAVE (1U<<26U)
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#define CPUID_ECX_OSXSAVE (1U<<27U)
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#define CPUID_ECX_AVX (1U<<28U)
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#define CPUID_ECX_HV (1U<<31U)
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#define CPUID_EDX_FPU (1U<<0U)
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#define CPUID_EDX_VME (1U<<1U)
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#define CPUID_EDX_DE (1U<<2U)
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#define CPUID_EDX_PSE (1U<<3U)
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#define CPUID_EDX_TSC (1U<<4U)
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#define CPUID_EDX_MSR (1U<<5U)
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#define CPUID_EDX_PAE (1U<<6U)
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#define CPUID_EDX_MCE (1U<<7U)
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#define CPUID_EDX_CX8 (1U<<8U)
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#define CPUID_EDX_APIC (1U<<9U)
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#define CPUID_EDX_SEP (1U<<11U)
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#define CPUID_EDX_MTRR (1U<<12U)
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#define CPUID_EDX_PGE (1U<<13U)
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#define CPUID_EDX_MCA (1U<<14U)
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#define CPUID_EDX_CMOV (1U<<15U)
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#define CPUID_EDX_PAT (1U<<16U)
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#define CPUID_EDX_PSE36 (1U<<17U)
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#define CPUID_EDX_PSN (1U<<18U)
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#define CPUID_EDX_CLF (1U<<19U)
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#define CPUID_EDX_DTES (1U<<21U)
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#define CPUID_EDX_ACPI (1U<<22U)
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#define CPUID_EDX_MMX (1U<<23U)
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#define CPUID_EDX_FXSR (1U<<24U)
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#define CPUID_EDX_SSE (1U<<25U)
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#define CPUID_EDX_SSE2 (1U<<26U)
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#define CPUID_EDX_SS (1U<<27U)
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#define CPUID_EDX_HTT (1U<<28U)
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#define CPUID_EDX_TM1 (1U<<29U)
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#define CPUID_EDX_IA64 (1U<<30U)
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#define CPUID_EDX_PBE (1U<<31U)
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/* CPUID.07H:EBX.FSGSBASE*/
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#define CPUID_EBX_FSGSBASE (1U<<0U)
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/* CPUID.07H:EBX.TSC_ADJUST*/
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#define CPUID_EBX_TSC_ADJ (1U<<1U)
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/* CPUID.07H:EBX.SGX */
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#define CPUID_EBX_SGX (1U<<2U)
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/* CPUID.07H:EBX.SMEP*/
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#define CPUID_EBX_SMEP (1U<<7U)
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/* CPUID.07H:EBX.MPX */
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#define CPUID_EBX_MPX (1U<<14U)
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/* CPUID.07H:EBX.SMAP*/
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#define CPUID_EBX_SMAP (1U<<20U)
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/* CPUID.07H:ECX.UMIP */
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#define CPUID_ECX_UMIP (1U<<2U)
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/* CPUID.07H:ECX.PKE */
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#define CPUID_ECX_PKE (1U<<3U)
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/* CPUID.07H:ECX.CET_SS */
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#define CPUID_ECX_CET_SS (1U<<7U)
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/* CPUID.07H:ECX.LA57 */
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#define CPUID_ECX_LA57 (1U<<16U)
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/* CPUID.07H:ECX.SGX_LC*/
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#define CPUID_ECX_SGX_LC (1U<<30U)
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/* CPUID.07H:ECX.PKS*/
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#define CPUID_ECX_PKS (1U<<31U)
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/* CPUID.07H:EDX.CET_IBT */
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#define CPUID_EDX_CET_IBT (1U<<20U)
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/* CPUID.07H:EDX.IBRS_IBPB*/
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#define CPUID_EDX_IBRS_IBPB (1U<<26U)
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/* CPUID.07H:EDX.STIBP*/
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#define CPUID_EDX_STIBP (1U<<27U)
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/* CPUID.80000001H:EDX.Page1GB*/
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#define CPUID_EDX_PAGE1GB (1U<<26U)
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/* CPUID.07H:EBX.INVPCID*/
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#define CPUID_EBX_INVPCID (1U<<10U)
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/* CPUID.07H:EBX.PQM */
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#define CPUID_EBX_PQM (1U<<12U)
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/* CPUID.07H:EBX.PQE */
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#define CPUID_EBX_PQE (1U<<15U)
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/* CPUID.07H:EBX.INTEL_PROCESSOR_TRACE */
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#define CPUID_EBX_PROC_TRC (1U<<25U)
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/* CPUID.01H:ECX.PCID*/
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#define CPUID_ECX_PCID (1U<<17U)
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/* CPUID.0DH.EAX.XCR0_BNDREGS */
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#define CPUID_EAX_XCR0_BNDREGS (1U<<3U)
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/* CPUID.0DH.EAX.XCR0_BNDCSR */
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#define CPUID_EAX_XCR0_BNDCSR (1U<<4U)
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/* CPUID.0DH.ECX.CET_U_STATE */
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#define CPUID_ECX_CET_U_STATE (1U<<11U)
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/* CPUID.0DH.ECX.CET_S_STATE */
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#define CPUID_ECX_CET_S_STATE (1U<<12U)
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/* CPUID.12H.EAX.SGX1 */
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#define CPUID_EAX_SGX1 (1U<<0U)
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/* CPUID.12H.EAX.SGX2 */
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#define CPUID_EAX_SGX2 (1U<<1U)
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/* CPUID.19H.EBX.KL_AES_ENABLED */
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#define CPUID_EBX_KL_AES_EN (1U<<0U)
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/* CPUID.19H.EBX.KL_BACKUP_MSR */
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#define CPUID_EBX_KL_BACKUP_MSR (1U<<4U)
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/* CPUID.19H.ECX.KL_NOBACKUP */
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#define CPUID_ECX_KL_NOBACKUP (1U<<0U)
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/* CPUID.19H.ECX.KL_RANDOM_KS */
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#define CPUID_ECX_KL_RANDOM_KS (1U<<1U)
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/* CPUID.80000001H.EDX.XD_BIT_AVAILABLE */
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#define CPUID_EDX_XD_BIT_AVIL (1U<<20U)
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/* CPUID source operands */
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#define CPUID_VENDORSTRING 0U
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#define CPUID_FEATURES 1U
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#define CPUID_TLB 2U
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#define CPUID_SERIALNUM 3U
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#define CPUID_LEAF_CACHE_TOPOLOGY 4U
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#define CPUID_EXTEND_FEATURE 7U
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#define CPUID_XSAVE_FEATURES 0xDU
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#define CPUID_RDT_ALLOCATION 0x10U
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#define CPUID_MAX_EXTENDED_FUNCTION 0x80000000U
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#define CPUID_EXTEND_FUNCTION_1 0x80000001U
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#define CPUID_EXTEND_FUNCTION_2 0x80000002U
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#define CPUID_EXTEND_FUNCTION_3 0x80000003U
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#define CPUID_EXTEND_FUNCTION_4 0x80000004U
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#define CPUID_EXTEND_INVA_TSC 0x80000007U
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#define CPUID_EXTEND_ADDRESS_SIZE 0x80000008U
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static inline void cpuid_subleaf(uint32_t leaf, uint32_t subleaf,
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uint32_t *eax, uint32_t *ebx,
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uint32_t *ecx, uint32_t *edx)
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{
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/* Execute CPUID instruction and save results */
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asm volatile("cpuid":"=a"(*eax), "=b"(*ebx),
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"=c"(*ecx), "=d"(*edx)
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: "a" (leaf), "c" (subleaf)
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: "memory");
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}
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#endif /* CPUID_H_ */
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