mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-08-16 07:15:21 +00:00
181de19cba
V4: - Renamed members for struct pcibar and changed code accordingly V3: - Do not use ASSERT - Use EPT_XX defines when claling ept_mr_add - Report 64-bit MMIO physical bar to UOS as 32-bit virtual bar (assume bar size is always less than 4GB), which removed quite some of 64-bit bar handling code Reviewed-by: Anthony Xu <anthony.xu@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com> Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
154 lines
4.2 KiB
C
154 lines
4.2 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef PCI_PRIV_H_
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#define PCI_PRIV_H_
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#include <hv_debug.h>
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#include "vpci.h"
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#define PCIM_BAR_MEM_BASE 0xfffffff0U
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#define PCI_BAR_BASE(val) ((val) & PCIM_BAR_MEM_BASE)
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#define PCI_BAR(base, type) ((base) | (type))
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#define PCI_BUS(bdf) (((bdf) >> 8) & 0xFFU)
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#define PCI_SLOT(bdf) (((bdf) >> 3) & 0x1FU)
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#define PCI_FUNC(bdf) ((bdf) & 0x07U)
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#define LOBYTE(w) ((uint8_t)((w) & 0xffU))
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#define PCI_BUSMAX 0xffU
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#define PCI_SLOTMAX 0x1fU
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#define PCI_FUNCMAX 0x7U
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#define MAXBUSES (PCI_BUSMAX + 1U)
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#define MAXSLOTS (PCI_SLOTMAX + 1U)
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#define MAXFUNCS (PCI_FUNCMAX + 1U)
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#define PCIR_VENDOR 0x00U
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#define PCIR_DEVICE 0x02U
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#define PCIR_COMMAND 0x04U
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#define PCIM_CMD_MEMEN 0x0002U
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#define PCIR_REVID 0x08U
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#define PCIR_SUBCLASS 0x0aU
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#define PCIR_CLASS 0x0bU
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#define PCIR_HDRTYPE 0x0eU
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#define PCIM_HDRTYPE_NORMAL 0x00U
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#define PCIM_MFDEV 0x80U
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#define PCIR_BARS 0x10U
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#define PCIR_BAR(x) (PCIR_BARS + ((x) * 4U))
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#define PCIM_BAR_MEM_SPACE 0U
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#define PCIC_BRIDGE 0x06U
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#define PCIS_BRIDGE_HOST 0x00U
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#define PCI_CONFIG_ADDR 0xcf8U
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#define PCI_CONFIG_DATA 0xcfcU
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#define PCI_CFG_ENABLE 0x80000000U
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void pci_vdev_cfg_handler(struct vpci *vpci, uint32_t in, uint16_t vbdf,
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uint32_t offset, uint32_t bytes, uint32_t *val);
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static inline uint8_t
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pci_vdev_read_cfg_u8(struct pci_vdev *vdev, uint32_t offset)
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{
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return (*(uint8_t *)(&vdev->cfgdata[0] + offset));
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}
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static inline uint16_t pci_vdev_read_cfg_u16(struct pci_vdev *vdev,
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uint32_t offset)
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{
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return (*(uint16_t *)(&vdev->cfgdata[0] + offset));
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}
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static inline uint32_t pci_vdev_read_cfg_u32(struct pci_vdev *vdev,
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uint32_t offset)
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{
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return (*(uint32_t *)(&vdev->cfgdata[0] + offset));
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}
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static inline void
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pci_vdev_write_cfg_u8(struct pci_vdev *vdev, uint32_t offset, uint8_t val)
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{
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*(uint8_t *)(vdev->cfgdata + offset) = val;
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}
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static inline void
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pci_vdev_write_cfg_u16(struct pci_vdev *vdev, uint32_t offset, uint16_t val)
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{
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*(uint16_t *)(vdev->cfgdata + offset) = val;
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}
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static inline void
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pci_vdev_write_cfg_u32(struct pci_vdev *vdev, uint32_t offset, uint32_t val)
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{
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*(uint32_t *)(vdev->cfgdata + offset) = val;
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}
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static inline uint32_t pci_vdev_read_cfg(struct pci_vdev *vdev,
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uint32_t offset, uint32_t bytes)
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{
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uint32_t val;
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switch (bytes) {
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case 1U:
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val = pci_vdev_read_cfg_u8(vdev, offset);
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break;
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case 2U:
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val = pci_vdev_read_cfg_u16(vdev, offset);
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break;
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default:
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val = pci_vdev_read_cfg_u32(vdev, offset);
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break;
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}
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return val;
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}
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static inline void pci_vdev_write_cfg(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t val)
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{
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switch (bytes) {
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case 1U:
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pci_vdev_write_cfg_u8(vdev, offset, val);
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break;
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case 2U:
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pci_vdev_write_cfg_u16(vdev, offset, val);
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break;
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default:
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pci_vdev_write_cfg_u32(vdev, offset, val);
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break;
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}
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}
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#endif /* PCI_PRIV_H_ */
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