acrn-hypervisor/hypervisor/include
dongshen 00ad3863a1 hv: maintain a per-pCPU array of vCPUs and handle posted interrupt IRQs
Maintain a per-pCPU array of vCPUs (struct acrn_vcpu *vcpu_array[CONFIG_MAX_VM_NUM]),
one VM cannot have multiple vCPUs share one pcpu, so we can utilize this property
and use the containing VM's vm_id as the index to the vCPU array:

 In create_vcpu(), we simply do:
   per_cpu(vcpu_array, pcpu_id)[vm->vm_id] = vcpu;

 In offline_vcpu():
   per_cpu(vcpu_array, pcpuid_from_vcpu(vcpu))[vcpu->vm->vm_id] = NULL;

so basically we use the containing VM's vm_id as the index to the vCPU array,
as well as the index of posted interrupt IRQ/vector pair that are assigned
to this vCPU:
  0: first vCPU and first posted interrupt IRQs/vector pair
  (POSTED_INTR_IRQ/POSTED_INTR_VECTOR)
  ...
  CONFIG_MAX_VM_NUM-1: last vCPU and last posted interrupt IRQs/vector pair
  ((POSTED_INTR_IRQ + CONFIG_MAX_VM_NUM - 1U)/(POSTED_INTR_VECTOR + CONFIG_MAX_VM_NUM - 1U)

In the posted interrupt handler, it will do the following:
 Translate the IRQ into a zero based index of where the vCPU
 is located in the vCPU list for current pCPU. Once the
 vCPU is found, we wake up the waiting thread and record
 this request as ACRN_REQUEST_EVENT

Tracked-On: #4506
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
Reviewed-by: Eddie Dong <eddie.dong@Intel.com>
Signed-off-by: dongshen <dongsheng.x.zhang@intel.com>
2020-04-15 13:47:22 +08:00
..
arch/x86 hv: maintain a per-pCPU array of vCPUs and handle posted interrupt IRQs 2020-04-15 13:47:22 +08:00
common hv: Introduce Global System Interrupt (GSI) into INTx Remapping 2020-03-25 09:36:18 +08:00
debug HV: correct ept page array usage 2020-03-12 14:56:34 +08:00
dm hv: vm: refine the devices unregistration sequence of vm shutdown 2020-04-08 10:13:37 +08:00
hw hv: vpci: handle the quirk part for pass through pci device cfg access in dm 2020-03-20 10:08:43 +08:00
lib hv: list: rename list_entry to container_of 2020-03-31 10:57:47 +08:00
public hv: vpci: handle the quirk part for pass through pci device cfg access in dm 2020-03-20 10:08:43 +08:00