Li, Fei1 05a4ee8074 hv: cpu: refine secondary cpu start up ... 1) add a write memory barrier after setting pcpu_sync to one to let this change visible to AP immediately. 2) there's only BSP will set pcpu_sync, so there's no memory order issue between CPUs. Tracked-On: #1842 Signed-off-by: Li, Fei1 <fei1.li@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2019-07-11 09:15:47 +08:00
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x86	hv: cpu: refine secondary cpu start up	2019-07-11 09:15:47 +08:00