Files
acrn-hypervisor/hypervisor/arch/x86
Li, Fei1 05a4ee8074 hv: cpu: refine secondary cpu start up
1) add a write memory barrier after setting pcpu_sync to one to let this change
visible to AP immediately.
2) there's only BSP will set pcpu_sync, so there's no memory order issue between CPUs.

Tracked-On: #1842
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
2019-07-11 09:15:47 +08:00
..
2019-05-07 09:10:13 +08:00
2019-07-09 10:36:44 +08:00
2019-06-14 14:22:51 +08:00
2019-05-07 09:10:13 +08:00
2019-06-20 09:32:55 +08:00
2019-07-11 09:15:47 +08:00
2019-02-22 13:14:36 +08:00
2019-06-20 09:32:55 +08:00
2019-02-22 13:14:36 +08:00
2019-05-08 16:57:46 +08:00
2019-06-25 20:09:21 +08:00
2019-05-07 09:10:13 +08:00