mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-05-02 13:44:00 +00:00
05ad6d6628
This patch fixes the following issue pointed by Xiangyang and Junjie.
There are some macro arguments acting as formal parameter names.
Drop such arguments since they make no difference to the expanded
implementation and they might confuse some developers.
Here is an example.
'ptr' is dropped in this patch, which is acting as a formal parameter
name and make no difference to the expanded implementation.
-#define build_atomic_load(name, size, type, ptr) \
+#define build_atomic_load(name, size, type) \
static inline type name(const volatile type *ptr) \
{ \
type ret; \
asm volatile("mov" size " %1,%0" \
: "=r" (ret) \
: "m" (*ptr) \
: "cc", "memory"); \
return ret; \
}
Some minor coding style fixes are also included in this patch.
- use TAB for the alignment rather than mixing TAB with space
- fix some typo in the comments
Tracked-On: #861
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
306 lines
8.6 KiB
C
306 lines
8.6 KiB
C
/*-
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* Copyright (c) 1998 Doug Rabson
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* Copyright (c) 2017 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef BITS_H
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#define BITS_H
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#include <cpu.h>
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/**
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*
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* INVALID_BIT_INDEX means when input paramter is zero,
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* bit operations function can't find bit set and return
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* the invalid bit index directly.
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*
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**/
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#define INVALID_BIT_INDEX 0xffffU
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/**
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*
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* fls32 - Find the Last (most significant) bit Set in value and
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* return the bit index of that bit.
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*
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* Bits are numbered starting at 0,the least significant bit.
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* A return value of INVALID_BIT_INDEX means return value is
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* invalid bit index when the input argument was zero.
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*
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* Examples:
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* fls32 (0x0) = INVALID_BIT_INDEX
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* fls32 (0x01) = 0
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* fls32 (0x80) = 7
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* ...
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* fls32 (0x80000001) = 31
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*
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* @param value: 'uint32_t' type value
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*
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* @return value: zero-based bit index, INVALID_BIT_INDEX means
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* when 'value' was zero, bit operations function can't find bit
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* set and return the invalid bit index directly.
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*
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* **/
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static inline uint16_t fls32(uint32_t value)
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{
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uint32_t ret = 0U;
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if (value == 0U) {
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return (INVALID_BIT_INDEX);
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}
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asm volatile("bsrl %1,%0"
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: "=r" (ret)
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: "rm" (value));
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return (uint16_t)ret;
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}
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static inline uint16_t fls64(uint64_t value)
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{
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uint64_t ret = 0UL;
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if (value == 0UL) {
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return (INVALID_BIT_INDEX);
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}
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asm volatile("bsrq %1,%0"
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: "=r" (ret)
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: "rm" (value));
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return (uint16_t)ret;
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}
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/**
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*
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* ffs64 - Find the First (least significant) bit Set in value(Long type)
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* and return the index of that bit.
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*
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* Bits are numbered starting at 0,the least significant bit.
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* A return value of INVALID_BIT_INDEX means that the return value is the inalid
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* bit index when the input argument was zero.
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*
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* Examples:
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* ffs64 (0x0) = INVALID_BIT_INDEX
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* ffs64 (0x01) = 0
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* ffs64 (0xf0) = 4
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* ffs64 (0xf00) = 8
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* ...
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* ffs64 (0x8000000000000001) = 0
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* ffs64 (0xf000000000000000) = 60
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*
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* @param value: 'unsigned long' type value
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*
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* @return value: zero-based bit index, INVALID_BIT_INDEX means
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* when 'value' was zero, bit operations function can't find bit
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* set and return the invalid bit index directly.
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*
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* **/
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static inline uint16_t ffs64(uint64_t value)
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{
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uint64_t ret = 0UL;
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if (value == 0UL) {
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return (INVALID_BIT_INDEX);
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}
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asm volatile("bsfq %1,%0"
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: "=r" (ret)
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: "rm" (value));
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return (uint16_t)ret;
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}
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/*bit scan forward for the least significant bit '0'*/
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static inline uint16_t ffz64(uint64_t value)
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{
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return ffs64(~value);
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}
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/*
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* find the first zero bit in a uint64_t array.
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* @pre: the size must be multiple of 64.
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*/
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static inline uint64_t ffz64_ex(const uint64_t *addr, uint64_t size)
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{
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uint64_t idx;
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for (idx = 0UL; (idx << 6U) < size; idx++) {
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if (addr[idx] != ~0UL)
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return (idx << 6U) + ffz64(addr[idx]);
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}
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return size;
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}
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/**
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* Counts leading zeros.
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*
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* The number of leading zeros is defined as the number of
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* most significant bits which are not '1'. E.g.:
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* clz(0x80000000)==0
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* clz(0x40000000)==1
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* ...
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* clz(0x00000001)==31
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* clz(0x00000000)==32
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*
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* @param value:The 32 bit value to count the number of leading zeros.
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*
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* @return The number of leading zeros in 'value'.
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*/
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static inline uint16_t clz(uint32_t value)
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{
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if (value == 0U) {
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return 32U;
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} else {
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return (31U - fls32(value));
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}
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}
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/**
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* Counts leading zeros (64 bit version).
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*
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* @param value:The 64 bit value to count the number of leading zeros.
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*
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* @return The number of leading zeros in 'value'.
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*/
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static inline uint16_t clz64(uint64_t value)
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{
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if (value == 0UL) {
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return 64U;
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} else {
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return (63U - fls64(value));
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}
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}
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/*
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* (*addr) |= (1UL<<nr);
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* Note:Input parameter nr shall be less than 64.
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* If nr>=64, it will be truncated.
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*/
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#define build_bitmap_set(name, op_len, op_type, lock) \
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static inline void name(uint16_t nr_arg, volatile op_type *addr) \
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{ \
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uint16_t nr; \
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nr = nr_arg & ((8U * sizeof(op_type)) - 1U); \
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asm volatile(lock "or" op_len " %1,%0" \
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: "+m" (*addr) \
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: "r" ((op_type)(1UL<<nr)) \
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: "cc", "memory"); \
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}
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build_bitmap_set(bitmap_set_nolock, "q", uint64_t, "")
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build_bitmap_set(bitmap_set_lock, "q", uint64_t, BUS_LOCK)
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build_bitmap_set(bitmap32_set_nolock, "l", uint32_t, "")
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build_bitmap_set(bitmap32_set_lock, "l", uint32_t, BUS_LOCK)
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/*
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* (*addr) &= ~(1UL<<nr);
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* Note:Input parameter nr shall be less than 64.
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* If nr>=64, it will be truncated.
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*/
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#define build_bitmap_clear(name, op_len, op_type, lock) \
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static inline void name(uint16_t nr_arg, volatile op_type *addr) \
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{ \
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uint16_t nr; \
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nr = nr_arg & ((8U * sizeof(op_type)) - 1U); \
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asm volatile(lock "and" op_len " %1,%0" \
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: "+m" (*addr) \
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: "r" ((op_type)(~(1UL<<(nr)))) \
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: "cc", "memory"); \
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}
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build_bitmap_clear(bitmap_clear_nolock, "q", uint64_t, "")
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build_bitmap_clear(bitmap_clear_lock, "q", uint64_t, BUS_LOCK)
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build_bitmap_clear(bitmap32_clear_nolock, "l", uint32_t, "")
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build_bitmap_clear(bitmap32_clear_lock, "l", uint32_t, BUS_LOCK)
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/*
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* return !!((*addr) & (1UL<<nr));
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* Note:Input parameter nr shall be less than 64. If nr>=64, it will
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* be truncated.
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*/
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static inline bool bitmap_test(uint16_t nr_arg, volatile uint64_t *addr)
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{
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uint16_t nr;
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int32_t ret=0;
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nr = nr_arg & 0x3fU;
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asm volatile("btq %q2,%1\n\tsbbl %0, %0"
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: "=r" (ret), "=m" (*addr)
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: "r" ((uint64_t)nr)
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: "cc", "memory");
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return (ret != 0);
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}
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static inline bool bitmap32_test(uint16_t nr_arg, volatile uint32_t *addr)
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{
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uint16_t nr;
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int32_t ret=0;
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nr = nr_arg & 0x1fU;
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asm volatile("btl %2,%1\n\tsbbl %0, %0"
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: "=r" (ret), "=m" (*addr)
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: "r" ((uint32_t)nr)
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: "cc", "memory");
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return (ret != 0);
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}
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/*
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* bool ret = (*addr) & (1UL<<nr);
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* (*addr) |= (1UL<<nr);
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* return ret;
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* Note:Input parameter nr shall be less than 64. If nr>=64, it
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* will be truncated.
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*/
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#define build_bitmap_testandset(name, op_len, op_type, lock) \
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static inline bool name(uint16_t nr_arg, volatile op_type *addr) \
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{ \
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uint16_t nr; \
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int32_t ret=0; \
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nr = nr_arg & ((8U * sizeof(op_type)) - 1U); \
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asm volatile(lock "bts" op_len " %2,%1\n\tsbbl %0,%0" \
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: "=r" (ret), "=m" (*addr) \
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: "r" ((op_type)nr) \
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: "cc", "memory"); \
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return (ret != 0); \
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}
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build_bitmap_testandset(bitmap_test_and_set_nolock, "q", uint64_t, "")
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build_bitmap_testandset(bitmap_test_and_set_lock, "q", uint64_t, BUS_LOCK)
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build_bitmap_testandset(bitmap32_test_and_set_nolock, "l", uint32_t, "")
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build_bitmap_testandset(bitmap32_test_and_set_lock, "l", uint32_t, BUS_LOCK)
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/*
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* bool ret = (*addr) & (1UL<<nr);
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* (*addr) &= ~(1UL<<nr);
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* return ret;
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* Note:Input parameter nr shall be less than 64. If nr>=64,
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* it will be truncated.
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*/
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#define build_bitmap_testandclear(name, op_len, op_type, lock) \
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static inline bool name(uint16_t nr_arg, volatile op_type *addr) \
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{ \
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uint16_t nr; \
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int32_t ret=0; \
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nr = nr_arg & ((8U * sizeof(op_type)) - 1U); \
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asm volatile(lock "btr" op_len " %2,%1\n\tsbbl %0,%0" \
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: "=r" (ret), "=m" (*addr) \
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: "r" ((op_type)nr) \
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: "cc", "memory"); \
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return (ret != 0); \
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}
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build_bitmap_testandclear(bitmap_test_and_clear_nolock, "q", uint64_t, "")
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build_bitmap_testandclear(bitmap_test_and_clear_lock, "q", uint64_t, BUS_LOCK)
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build_bitmap_testandclear(bitmap32_test_and_clear_nolock, "l", uint32_t, "")
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build_bitmap_testandclear(bitmap32_test_and_clear_lock, "l", uint32_t, BUS_LOCK)
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#endif /* BITS_H*/
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