Haiwei Li 5283c147ef hv: pci: Add guest cfg header access handling of type 1 device ...

When guests resume form s3, an error occurs in guest:

```
pcieport 0000:00:1c.0: refused to change power state from D0 to D3hot
```

PCI bridge (type 1 device) will access configuration space header but
now acrn is not supported. So add handling support.

Tracked-On: #8623
Signed-off-by: Haiwei Li <haiwei.li@intel.com>

2024-06-27 11:26:09 +08:00

..

hw_thermal.h

hv: enable thermal lvt interrupt

2024-05-16 09:40:32 +08:00

hw_timer.h

hv/mod_timer: make timer into an arch-independent module

2021-05-18 16:43:28 +08:00

pci.h

hv: pci: Add guest cfg header access handling of type 1 device

2024-06-27 11:26:09 +08:00